Abstract: A PLD is disclosed that uses vector routing between components. A vector routing path is coupled between the components and includes a group of wires for routing a group of bits as one vector so that all bits in the vector are switched at once and as a group by a single set of control signals. Vector switch boxes are used to switch entire vectors of a predetermined bit width and a fixed-bit order. The vector routing may be between components in a vector domain, within vector-based components, or between components in a PLD domain and a vector domain. The vector routing path may allow for time-division multiplexing. For example, different components may use the same vector routing path during different time slices. The vector routing path may be dynamically segmented. Dynamic segmentation allows different portions of the same vector routing path to be used simultaneously by different components. A component may be coupled to multiple vector routing paths through a multiplexer.

Abstract: A method of routing input signals in a programmable logic device (PLD) is disclosed. In a PLD having a PLD domain and a vector domain, input signals from the PLD domain are typically routed to the vector domain through an interface. The interface, however, often comprises a limited number of conductors and restricts the amount of data that can be directly transmitted to the vector domain. The disclosed method may be utilized to design an input switching unit that may use PLD-domain resources to route the input signals according to the time periods (or states) in which they operate. The input switching unit may comprise one or more multiplexers that are used to route the input signals in a time-multiplexed manner. As a result of the disclosed method, the amount of data that can be transmitted through the interface is maximized.

Abstract: A programmable logic device (PLD) is disclosed that includes a state machine integrated into a block memory. The state machine includes state machine logic and memory elements from the block memory. The state machine logic and memory elements together may be used as an instruction unit of a processor. In such a case, the instruction unit is coupled to a processor execution unit to form a high-performance, embedded processor within a PLD.

Abstract: To locate soft cells in a memory cell array, a known logic pattern is written in the memory array. The word lines for the array are then sequentially subjected to a nonstandard test signal such as a slowly varying voltage. Word lines are returned to VCC and the array is then interrogated to identify memory cells which have flipped logic states. These cells are identified as soft or potentially defective cells. The process can be repeated with the logically opposite logic pattern being initially stored in the array. Apparatus is provided for implementing this process on a standard RAM memory cell array. An access pad is added for receipt of an externally generated test signal. A control circuit selectively couples the test signal to the word lines for the memory array.