Patents by Inventor David J. Zimmerman
David J. Zimmerman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11200176Abstract: A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.Type: GrantFiled: September 1, 2020Date of Patent: December 14, 2021Assignee: Intel CorporationInventors: Raj K. Ramanujan, Glenn J Hinton, David J. Zimmerman
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Publication number: 20210056035Abstract: A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.Type: ApplicationFiled: September 1, 2020Publication date: February 25, 2021Inventors: Raj K. RAMANUJAN, Glenn J. HINTON, David J. ZIMMERMAN
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Patent number: 10795823Abstract: A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.Type: GrantFiled: December 20, 2011Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Raj K Ramanujan, Glenn J Hinton, David J Zimmerman
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Patent number: 10719443Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: GrantFiled: March 25, 2019Date of Patent: July 21, 2020Assignee: Intel CorporationInventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
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Patent number: 10541009Abstract: Devices, systems, and methods having increased efficiency selective writing to memory are disclosed and described. A memory controller, upon receiving a dirty data segment, performs a read-modify-write to retrieve a corresponding data line from memory, saves a copy of the data line, merges the dirty data segment into the appropriate location in the data line to create a modified data line, and generates a write mask from the modified data line and the copy of the data line.Type: GrantFiled: December 28, 2017Date of Patent: January 21, 2020Assignee: Intel CorporationInventors: David J. Zimmerman, Robert M. Ellis, Rajesh Sundaram
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Patent number: 10504591Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.Type: GrantFiled: July 13, 2018Date of Patent: December 10, 2019Assignee: Intel CorporationInventors: Shekoufeh Qawami, Rajesh Sundaram, David J. Zimmerman, Blaise Fanning
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Publication number: 20190220406Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: ApplicationFiled: March 25, 2019Publication date: July 18, 2019Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Kai CHENG, Taarinya POLEPEDDI, Camille C. RAAD, David J. ZIMMERMAN, Muthukumar P. SWAMINATHAN, Dimitrios ZIAKAS, Mohan J. KUMAR, Bassam N. COURY, Glenn J. HINTON
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Patent number: 10347354Abstract: A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.Type: GrantFiled: October 13, 2016Date of Patent: July 9, 2019Assignee: Intel CorporationInventor: David J. Zimmerman
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Patent number: 10241912Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: GrantFiled: March 13, 2017Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
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Publication number: 20190057737Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.Type: ApplicationFiled: July 13, 2018Publication date: February 21, 2019Inventors: Shekoufeh QAWAMI, Rajesh SUNDARAM, David J. ZIMMERMAN, Blaise FANNING
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Publication number: 20190035437Abstract: Devices, systems, and methods having increased efficiency selective writing to memory are disclosed and described. A memory controller, upon receiving a dirty data segment, performs a read-modify-write to retrieve a corresponding data line from memory, saves a copy of the data line, merges the dirty data segment into the appropriate location in the data line to create a modified data line, and generates a write mask from the modified data line and the copy of the data line.Type: ApplicationFiled: December 28, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: DAVID J. ZIMMERMAN, ROBERT M. ELLIS, RAJESH SUNDARAM
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Patent number: 10026475Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.Type: GrantFiled: October 8, 2015Date of Patent: July 17, 2018Assignee: Intel CorporationInventors: Shekoufeh Qawami, Rajesh Sundaram, David J. Zimmerman, Blaise Fanning
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Patent number: 10025737Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.Type: GrantFiled: June 4, 2015Date of Patent: July 17, 2018Assignee: Intel CorporationInventors: Shekoufeh Qawami, Rajesh Sundaram, David J. Zimmerman, Robert W. Faber
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Patent number: 9922725Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets.Type: GrantFiled: December 2, 2016Date of Patent: March 20, 2018Assignee: INTEL CORPORATIONInventors: Bruce Querbach, William K. Lui, David G. Ellis, David J. Zimmerman, Theodore Z. Schoenborn, Christopher W. Hampson, Ifar Wan, Yulan Zhang
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Publication number: 20170249250Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: ApplicationFiled: March 13, 2017Publication date: August 31, 2017Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Kai CHENG, Taarinya POLEPEDDI, Camille C. RAAD, David J. ZIMMERMAN, Muthukumar P. SWAMINATHAN, Dimitrios ZIAKAS, Mohan J. KUMAR, Bassam N. COURY, Glenn J. HINTON
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Publication number: 20170169900Abstract: A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.Type: ApplicationFiled: October 13, 2016Publication date: June 15, 2017Inventor: David J. Zimmerman
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Publication number: 20170084351Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets. Other aspects are described herein.Type: ApplicationFiled: December 2, 2016Publication date: March 23, 2017Inventors: Bruce QUERBACH, William K. LUI, David G. ELLIS, David J. ZIMMERMAN, Theodore Z. SCHOENBORN, Christopher W. HAMPSON, Ifar WAN, Yulan ZHANG
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Patent number: 9600416Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: GrantFiled: September 30, 2011Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
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Patent number: 9564245Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.Type: GrantFiled: December 26, 2013Date of Patent: February 7, 2017Assignee: INTEL CORPORATIONInventors: Bruce Querbach, Theodore Z. Schoenborn, David J. Zimmerman, David G. Ellis, Christopher W. Hampson, Ifar Wan, Yulan Zhang, Ramakrishna Mallela, William K. Lui
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Patent number: 9548137Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.Type: GrantFiled: June 30, 2014Date of Patent: January 17, 2017Assignee: INTEL CORPORATIONInventors: Bruce Querbach, William K. Lui, David G. Ellis, David J. Zimmerman, Theodore Z. Schoenborn, Christopher W. Hampson, Ifar Wan, Yulan Zhang