Patents by Inventor David J. Zimmerman

David J. Zimmerman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10593213
    Abstract: Customization of sharing of rides can involve the grouping of passengers in vehicles according to objective and subjective parameters and preferences. In some embodiments, vehicles or other components of the system are equipped to identify and compare information about users of the system using biometric scanning. In some embodiments, fares for rideshares can be tied to a projected quality or desirability of the rideshare for a user or users of the system.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 17, 2020
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Jennifer L. Copeland, Suzanne M. Fisi, Simone O. Harvey, David C. Hatch, Muhammad Farukh Munir, Aaron Francis Colfax Petrik, Darrell L. Suen, Timothy R. Ward, Steven J. Wirt, Ryan J. Wyler, Nancy B. Zimmerman, Chris Kalaboukis
  • Patent number: 10541009
    Abstract: Devices, systems, and methods having increased efficiency selective writing to memory are disclosed and described. A memory controller, upon receiving a dirty data segment, performs a read-modify-write to retrieve a corresponding data line from memory, saves a copy of the data line, merges the dirty data segment into the appropriate location in the data line to create a modified data line, and generates a write mask from the modified data line and the copy of the data line.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: David J. Zimmerman, Robert M. Ellis, Rajesh Sundaram
  • Patent number: 10504591
    Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Shekoufeh Qawami, Rajesh Sundaram, David J. Zimmerman, Blaise Fanning
  • Patent number: 10450645
    Abstract: A coating system for coating a part (10), such as a turbine blade or vane, has a mask (14) positioned adjacent to a first portion (16) of the part (10) to be coated and a mechanism (30) for moving the mask (14) relative to the part (10). The mechanism (30) may be a gear mechanism or a magnetic mechanism.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: October 22, 2019
    Assignee: United Technologies Corporation
    Inventors: James W. Neal, David A. Litton, Russell A. Beers, Benjamin Joseph Zimmerman, Michael J. Maloney
  • Patent number: 10446373
    Abstract: In an embodiment of the invention there is a cyclotronic actuator utilizing a high-voltage plasma driver connected to a first electrode. A second electrode is grounded and the two are isolated from each other by a dielectric plate. A magnet is positioned beneath the dielectric plate such that a coaxial dielectric barrier discharge plasma is formed outwardly between the first electrode across the dielectric plate. The magnet positioned beneath the dielectric plate introduces a magnetic field transverse to the plasma current path, such that the plasma discharge discharges radially and the local magnetic field is oriented vertically in a direction perpendicular to the dielectric plate to create a Lorentz Force, which forces the plasma discharge to move radially outwardly in a curved radial streamer mode pattern.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 15, 2019
    Assignee: CU Aerospace, LLC
    Inventors: Joseph W. Zimmerman, David L. Carroll, Phillip J. Ansell, Georgi Hristov
  • Publication number: 20190296360
    Abstract: An electrode material useful as a dry in place deposit comprising at least one metal chelating polymer; an active material capable of reversibly intercalating lithium ions; a plurality of electrical conductor particles; a binder polymer. The electrode material is formed into a slurry using a non-aqueous solvent. The metal chelating polymer may be a reaction product of a polyphenolic polymer; an aldehyde, a ketone, or mixtures thereof; and an amine. The electrode material slurry is deposited on a current collector and dried to form a positive electrode in a secondary lithium ion battery. The deposited electrode material has high flexibility, adhesion to the current collector, resistance to electrolyte damage, and low electrical resistance. The electrode material forms a superior positive electrode at a relatively low additional cost and with no increase in process complexity.
    Type: Application
    Filed: June 5, 2019
    Publication date: September 26, 2019
    Inventors: John L. Zimmerman, John D. McGee, Andrew M. Dahl, John J. Comoford, David R. McCormick, Gregory T. Donaldson
  • Publication number: 20190246482
    Abstract: In an embodiment of the invention there is a cyclotronic actuator utilizing a high-voltage plasma driver connected to a first electrode. A second electrode is grounded and the two are isolated from each other by a dielectric plate. A magnet is positioned beneath the dielectric plate such that a coaxial dielectric barrier discharge plasma is formed outwardly between the first electrode across the dielectric plate. The magnet positioned beneath the dielectric plate introduces a magnetic field transverse to the plasma current path, such that the plasma discharge discharges radially and the local magnetic field is oriented vertically in a direction perpendicular to the dielectric plate to create a Lorentz Force, which forces the plasma discharge to move radially outwardly in a curved radial streamer mode pattern.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 8, 2019
    Applicants: CU Aerospace, LLC, The Board of Trustees of the University of Illinois
    Inventors: Joseph W. Zimmerman, David L. Carroll, Phillip J. Ansell, Georgi Hristov
  • Publication number: 20190220406
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.
    Type: Application
    Filed: March 25, 2019
    Publication date: July 18, 2019
    Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Kai CHENG, Taarinya POLEPEDDI, Camille C. RAAD, David J. ZIMMERMAN, Muthukumar P. SWAMINATHAN, Dimitrios ZIAKAS, Mohan J. KUMAR, Bassam N. COURY, Glenn J. HINTON
  • Patent number: 10347354
    Abstract: A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventor: David J. Zimmerman
  • Patent number: 10332724
    Abstract: In an embodiment of the invention there is a cyclotronic actuator. The actuator is defined by having a high-voltage plasma driver connected to a first electrode. The first electrode is surrounded by a dielectric material. A second electrode is grounded and placed away from the first electrode, such that a plasma arc is formed between the pair of electrodes when the high-voltage plasma driver is activated. A ring magnet surrounding the second electrode is configured to introduce a magnetic field locally to the plasma arc. The plasma arc will then discharge in a radial direction. The magnet creates a local magnetic field oriented vertically in a direction parallel to the axisymmetric orientation of the first and second electrodes to create a Lorentz Force. The force causes the plasma arc to move in a tangential direction and causes the plasma arc to discharge out in a circular pattern.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 25, 2019
    Assignee: CU Aerospace, LLC
    Inventors: Joseph W. Zimmerman, David L. Carroll, Phillip J. Ansell, Georgi Hristov
  • Patent number: 10241912
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
  • Publication number: 20190057737
    Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.
    Type: Application
    Filed: July 13, 2018
    Publication date: February 21, 2019
    Inventors: Shekoufeh QAWAMI, Rajesh SUNDARAM, David J. ZIMMERMAN, Blaise FANNING
  • Publication number: 20190035437
    Abstract: Devices, systems, and methods having increased efficiency selective writing to memory are disclosed and described. A memory controller, upon receiving a dirty data segment, performs a read-modify-write to retrieve a corresponding data line from memory, saves a copy of the data line, merges the dirty data segment into the appropriate location in the data line to create a modified data line, and generates a write mask from the modified data line and the copy of the data line.
    Type: Application
    Filed: December 28, 2017
    Publication date: January 31, 2019
    Applicant: Intel Corporation
    Inventors: DAVID J. ZIMMERMAN, ROBERT M. ELLIS, RAJESH SUNDARAM
  • Patent number: 10025737
    Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Shekoufeh Qawami, Rajesh Sundaram, David J. Zimmerman, Robert W. Faber
  • Patent number: 10026475
    Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Shekoufeh Qawami, Rajesh Sundaram, David J. Zimmerman, Blaise Fanning
  • Patent number: 9922725
    Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: March 20, 2018
    Assignee: INTEL CORPORATION
    Inventors: Bruce Querbach, William K. Lui, David G. Ellis, David J. Zimmerman, Theodore Z. Schoenborn, Christopher W. Hampson, Ifar Wan, Yulan Zhang
  • Publication number: 20170249250
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.
    Type: Application
    Filed: March 13, 2017
    Publication date: August 31, 2017
    Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Kai CHENG, Taarinya POLEPEDDI, Camille C. RAAD, David J. ZIMMERMAN, Muthukumar P. SWAMINATHAN, Dimitrios ZIAKAS, Mohan J. KUMAR, Bassam N. COURY, Glenn J. HINTON
  • Publication number: 20170169900
    Abstract: A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.
    Type: Application
    Filed: October 13, 2016
    Publication date: June 15, 2017
    Inventor: David J. Zimmerman
  • Publication number: 20170084351
    Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets. Other aspects are described herein.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Inventors: Bruce QUERBACH, William K. LUI, David G. ELLIS, David J. ZIMMERMAN, Theodore Z. SCHOENBORN, Christopher W. HAMPSON, Ifar WAN, Yulan ZHANG
  • Patent number: 9600416
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton