Abstract: An improved method and apparatus for S/TEM sample preparation and analysis. Preferred embodiments of the present invention provide improved methods for TEM sample creation, especially for small geometry (<100 nm thick) TEM lamellae. Preferred embodiments of the present invention also provide an in-line process for S/TEM based metrology on objects such as integrated circuits or other structures fabricated on semiconductor wafer by providing methods to partially or fully automate TEM sample creation, to make the process of creating and analyzing TEM samples less labor intensive, and to increase throughput and reproducibility of TEM analysis.

Abstract: An improved method and apparatus for S/TEM sample preparation and analysis. Preferred embodiments of the present invention provide improved methods for TEM sample creation, especially for small geometry (<100 nm thick) TEM lamellae. Preferred embodiments of the present invention also provide an in-line process for S/TEM based metrology on objects such as integrated circuits or other structures fabricated on semiconductor wafer by providing methods to partially or fully automate TEM sample creation, to make the process of creating and analyzing TEM samples less labor intensive, and to increase throughput and reproducibility of TEM analysis.

Abstract: An improved method and apparatus for S/TEM sample preparation and analysis. Preferred embodiments of the present invention provide improved methods for TEM sample creation, especially for small geometry (<100 nm thick) TEM lamellae. Preferred embodiments of the present invention also provide an in-line process for S/TEM based metrology on objects such as integrated circuits or other structures fabricated on semiconductor wafer by providing methods to partially or fully automate TEM sample creation, to make the process of creating and analyzing TEM samples less labor intensive, and to increase throughput and reproducibility of TEM analysis.

Abstract: An improved method and apparatus for S/TEM sample preparation and analysis. Preferred embodiments of the present invention provide improved methods for TEM sample creation, especially for small geometry (<100 nm thick) TEM lamellae. Preferred embodiments of the present invention also provide an in-line process for S/TEM based metrology on objects such as integrated circuits or other structures fabricated on semiconductor wafer by providing methods to partially or fully automate TEM sample creation, to make the process of creating and analyzing TEM samples less labor intensive, and to increase throughput and reproducibility of TEM analysis.

Abstract: An improved method and apparatus for S/TEM sample preparation and analysis. Preferred embodiments of the present invention provide improved methods for TEM sample creation, especially for small geometry (<100 nm thick) TEM lamellae. Preferred embodiments of the present invention also provide an in-line process for S/TEM based metrology on objects such as integrated circuits or other structures fabricated on semiconductor wafer by providing methods to partially or fully automate TEM sample creation, to make the process of creating and analyzing TEM samples less labor intensive, and to increase throughput and reproducibility of TEM analysis.

Abstract: An improved method and apparatus for S/TEM sample preparation and analysis. Preferred embodiments of the present invention provide improved methods for TEM sample creation, especially for small geometry (<100 nm thick) TEM lamellae. Preferred embodiments of the present invention also provide an in-line process for S/TEM based metrology on objects such as integrated circuits or other structures fabricated on semiconductor wafer by providing methods to partially or fully automate TEM sample creation, to make the process of creating and analyzing TEM samples less labor intensive, and to increase throughput and reproducibility of TEM analysis.

Abstract: An improved method and apparatus for S/TEM sample preparation and analysis. Preferred embodiments of the present invention provide improved methods for TEM sample creation, especially for small geometry (<100 nm thick) TEM lamellae. Preferred embodiments of the present invention also provide an in-line process for S/TEM based metrology on objects such as integrated circuits or other structures fabricated on semiconductor wafer by providing methods to partially or fully automate TEM sample creation, to make the process of creating and analyzing TEM samples less labor intensive, and to increase throughput and reproducibility of TEM analysis.