Abstract: A computer-based method automatically synthesizes, optimizes and compiles high performance control logic using SRCMOS LOGIC ARRAY MACROS, abbreviated as SLAMs.

Abstract: A method and system for shape processing within an integrated circuit layout for parasitic capacitance estimation is disclosed. In accordance with the method and system of the present invention, a set of coordinates of an overlapping region formed by at least one interconnect is first identified. Subsequently, each metal layer present within the overlapping region is classified. Each interconnect edge present on each side of the overlapping region is then determined. Finally, a neighbor in a direction perpendicular to each side of the overlapping region is determined. By so doing, the parasitic capacitance between the overlapping region and its determined neighbors can be evaluated.

Abstract: A logic circuit family implements self-resetting CMOS logic array macros (SLAMs) which include a plurality of inputs to which a plurality of data input signals can be applied; a plurality of input buffers coupled to receive the input signals from the inputs; a NOR circuit coupled to receive the outputs of the input buffers and a pulsed logic timing signal synchronized within a predefined window with the arrival of the data input signals; an output buffer coupled to receive the output of the NOR circuit; and an output at which a data output signal is produced, with the output signal being a logical NOR of the data input signals; and with each of the NOR circuit, the plurality of input buffers, and the output buffer optionally having a separate reset input to reset it to a standby state. The SLAMs address the very high pressure on the performance of both control logic and control logic design systems.