Abstract: A method and processor are provided. The method includes storing a first value at a first field of a first cache tag line when a next occurrence of a first COF instruction is presumed to branch and when the end location of the first COF instruction is at a first location of memory, storing a second value at the first field to indicate the next occurrence of the first COF instruction is presumed to branch and when the end location of the first COF instruction is at a second location of memory. The processor includes an instruction cache having instruction data represented by a plurality of data segments and a prefetch unit. The prefetch unit is operable to receive a first data segment from the instruction cache and determine whether an end byte of a predicted taken COF instruction is present in the first data segment.

Abstract: Disclosed herein are exemplary techniques for generating trace information streams to facilitate the reconstruction of the instruction execution history of a processing device for a given time period. The linear instruction pointers or other representations of the instructions executed by a processing device are output as a trace information stream. When one or more translation lookaside buffers (TLBs) used by the processing device are modified by the addition of a new linear-to-physical translation and/or the eviction of an old linear-to-physical translation, a representation of the newly added translation entry, or, alternatively the evicted translation entry, is inserted into the trace information stream. In this manner, the context for the address mapping of the instruction pointers of the trace information stream is provided and, consequently, the execution instruction history of the processing device may be more fully reconstructed.

Abstract: The times-two (.times.2) through times-nine (.times.9) multiples of a supplied multi-digit BCD number are produced using one machine cycle for performing a set-up operation and thereafter one additional machine cycle for producing all the .times.2-.times.9 multiples. A multiples generating circuit in accordance with the invention comprises: (a) an operand-storing register (OSR); (b) a multiple-storing register (MSR); (c) a multiplexer having a first input coupled to the output of the operand-storing register (OSR) and a second input coupled to the output of the multiple-storing register (MSR); (d) a .times.3 unit having an input coupled to the output of the multiplexer and an output coupled to the input of the MSR; (e) a first .times.2 unit having an input coupled to the output of the OSR; (f) a second .times.2 unit having an input coupled to the output of the first .times.2 unit; (g) a third .times.2 unit having an input coupled to the output of the second .times.2 unit; (h) a fourth .times.