Patents by Inventor David Jaska

David Jaska has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7428719
    Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: September 23, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: David Jaska, Tan Du
  • Publication number: 20060117291
    Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.
    Type: Application
    Filed: January 17, 2006
    Publication date: June 1, 2006
    Inventors: David Jaska, Tan Du
  • Patent number: 7032204
    Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: David Jaska, Tan Du
  • Publication number: 20040225987
    Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.
    Type: Application
    Filed: June 8, 2004
    Publication date: November 11, 2004
    Inventors: David Jaska, Tan Du
  • Patent number: 6751784
    Abstract: The invention provides an algorithm for systematically determining and optimizing the physical implementation of an array of networks with a combination of matching series and parallel elements. Disclosed are the machine-implemented steps of defining the network in terms of a network value representing the sum of the elements. The network value is divided into an integer part and a proper fraction part. A partial quotient and residue are computed for the proper fraction part. Additional partial quotients and residues may be computed while the residue is significant. The physical implementation of the network is then described in terms of series and parallel elements represented by the integer part and the partial quotients. Also disclosed is a method of assembling a network from a combination of series and parallel elements. A network value consisting of an integer part and a proper fraction part are used to represent the network.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: June 15, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Tan Du, David Jaska
  • Publication number: 20040031002
    Abstract: The invention provides an algorithm for systematically determining and optimizing the physical implementation of an array of networks with a combination of matching series and parallel elements. Disclosed are the machine-implemented steps of defining the network in terms of a network value representing the sum of the elements. The network value is divided into an integer part and a proper fraction part. A partial quotient and residue are computed for the proper fraction part. Additional partial quotients and residues may be computed while the residue is significant. The physical implementation of the network is then described in terms of series and parallel elements represented by the integer part and the partial quotients. Also disclosed is a method of assembling a network from a combination of series and parallel elements. A network value consisting of an integer part and a proper fraction part are used to represent the network.
    Type: Application
    Filed: August 12, 2002
    Publication date: February 12, 2004
    Inventors: Tan Du, David Jaska