Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Abstract: A method for identifying select ones of insurance records which possess a favorable subrogation potential. The method includes receiving data indicative of a plurality of claims; automatically calculating a base score to identify select ones of the claims which demonstrate at least a given probability of expected subrogation recovery dependently upon the received data; automatically identifying risk factors for each of the select claims; and, automatically scoring each of the select claims dependently upon the base scores and identified risk factors to provide a value indicative of an expected subrogation recovery.

Abstract: A method for identifying select ones of insurance records which possess a favorable subrogation potential. The method includes receiving data indicative of a plurality of claims; automatically calculating a base score to identify select ones of the claims which demonstrate at least a given probability of expected subrogation recovery dependently upon the received data; automatically identifying risk factors for each of the select claims; and, automatically scoring each of the select claims dependently upon the base scores and identified risk factors to provide a value indicative of an expected subrogation recovery.

Abstract: A method for identifying select ones of insurance records which possess a favorable subrogation potential. The method includes receiving data indicative of a plurality of claims; automatically calculating a base score to identify select ones of the claims which demonstrate at least a given probability of expected subrogation recovery dependently upon the received data; automatically identifying risk factors for each of the select claims; and, automatically scoring each of the select claims dependently upon the base scores and identified risk factors to provide a value indicative of an expected subrogation recovery.

Abstract: A method for identifying select ones of insurance records which possess a favorable subrogation potential. The method includes receiving data indicative of a plurality of claims; automatically calculating a base score to identify select ones of the claims which demonstrate at least a given probability of expected subrogation recovery dependently upon the received data; automatically identifying risk factors for each of the select claims; and, automatically scoring each of the select claims dependently upon the base scores and identified risk factors to provide a value indicative of an expected subrogation recovery.

Abstract: A user interface for a cardiac rhythm management device programmer. A plurality of cardiac rhythm management device families can be listed according to device family or according to specific model names and/or model numbers. In addition, high-level information related to specific cardiac rhythm management devices can be listed by a second module. The second module can accessed through selection of a specific device family or model name and/or model number listed by the first module.

Abstract: A memory module for use in a two rank memory module system includes a plurality of memory devices and a control circuit. In one embodiment, the control circuit may be configured to generate a chip select signal that is provided to each of the memory devices. The chip select signal may be dependent upon assertions of a first bank chip select signal and a second bank chip select signal received from a memory controller. The control circuit may be further configured to generate an address signal that is provided to each of the memory devices. The address signal may be asserted dependent upon which of the first bank chip select signal and the second bank chip select signal are asserted.

Abstract: A memory expansion module with stacked memory packages. A memory module is implemented using stacked memory packages. Each of the stacked memory packages contains multiple memory chips, typically DRAMs (dynamic random access memory). The memory may be organized into multiple banks, wherein a given memory chip within a stacked memory package is part of one bank, while another memory chip in the same package is part of another bank. The memory module also includes a clock driver chip and a storage unit. The storage unit is configured to store module identification information, such as a serial number. The storage unit is also configured to store information correlating electrical contact pads on the module with individual signal pins on the stacked memory packages. This may allow an error to be quickly traced to a specific pin on a stacked memory package when an error is detected on the memory bus by an error correction subsystem.

Abstract: A memory module for expanding memory of a computer. The memory module comprises a printed circuit board including a connector edge having a plurality of contact pads configured to convey data signals, power and ground to and from said printed circuit board. The power and ground contact pads alternate along said connector edge with no more than four adjacent data signal contact pads without intervening power or ground contact pads. A plurality of memory devices mounted on the printed circuit board. A clock driver is coupled to each of the plurality of memory devices and is configured to receive a differential clock signal and to produce at least one single-ended clock signal for clocking the plurality of memory devices. The clock driver includes a phase-locked loop for phase-locking the at least one single-ended clock signal.

Abstract: A memory module test system with reduced driver output impedance. A test system includes a plurality of driver circuits, each of which is coupled to a transmission line on a loadboard. The loadboard includes a socket for insertion of the memory module to be tested. A test signal is generated and driven onto a transmission line by a driver circuit. A duplicate test signal is driven by a separate driver circuit onto a separate transmission line. The transmission lines carrying the test signal and duplicate test signal are electrically shorted on the loadboard. Electrically shorting these transmission lines effectively reduces their impedance by half. Multiple test signals generated by the test system are shorted in this manner in order to allow the electrical environment of the test system to more closely approximate that of the application environment of the tested memory module.