Patents by Inventor David Jerome Johnson

David Jerome Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Speculative pre-fetching additional line on cache miss if no request pending in out-of-order processor
    Patent number: 6643766
    Abstract: Speculative pre-fetching and pre-flushing of additional cache lines minimize cache miss latency and coherency check latency of an out of order instruction execution processor. A pre-fetch/pre-flush slot (DPRESLOT) is provided in a memory queue (MQUEUE) of the out-of-order execution processor. The DPRESLOT monitors the transactions between a system interface, e.g., the system bus, and an address reorder buffer slot (ARBSLOT) and/or between the system interface and a cache coherency check slot (CCCSLOT). When a cache miss is detected, the DPRESLOT causes one or more cache lines in addition to the data line, which caused the current cache miss, to be pre-fetched from the memory hierarchy into the cache memory (DCACHE) in anticipation that the additional data would be required in the near future.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: November 4, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gregg B Lesartre, David Jerome Johnson
  • Speculative pre-flush of data in an out-of-order execution processor system
    Patent number: 6408363
    Abstract: Speculative pre-fetching and pre-flushing of additional cache lines minimize cache miss latency and coherency check latency of an out of order instruction execution processor. A pre-fetch/pre-flush slot (DPRESLOT) is provided in a memory queue (MQUEUE) of the out-of-order execution processor. The DPRESLOT monitors the transactions between a system interface, e.g., the system bus, and an address reorder buffer slot (ARBSLOT) and/or between the system interface and a cache coherency check slot (CCCSLOT). When a cache miss is detected, the DPRESLOT causes one or more cache lines in addition to the data line, which caused the current cache miss, to be pre-fetched from the memory hierarchy into the cache memory (DCACHE) in anticipation that the additional data would be required in the near future.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: June 18, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Gregg B Lesartre, David Jerome Johnson