Abstract: An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for receiving and processing the data signal, which comprises data represented by a series of voltage state transitions, and pull-up and pull-down array calibration words, for generating and outputting a processed I/O output signal to the resistive element to output a substantially flat v/i response at switching of the data signal.

Abstract: An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for receiving and processing the data signal, which comprises data represented by a series of voltage state transitions, and pull-up and pull-down array calibration words, for generating and outputting a processed I/O output signal to the resistive element to output a substantially flat v/i response at switching of the data signal.

Abstract: An IO driver circuit incorporates an output stage control circuit that selectively configures an output stage for the IO driver circuit to operate as a thevenin termination whenever the IO driver circuit is receiving a signal from an input/output node to which the IO driver circuit is coupled. The output stage may include a plurality of branches, with each branch having a pull-up device and a pull-down device, and the output stage control circuit selectively activates the pull-up devices in a first subset of branches in the output stage while concurrently activating the pull-down devices in a second subset of branches, as well as while leaving the pull-up devices in the second subset of branches and the pull-down devices in the first subset of branches deactivated.

Abstract: An IO driver utilizes a slew rate boost circuit coupled to an IO driver circuit to improve the slew rate of the driver during transitions on the output of the driver. One or more additional output stages are coupled in parallel with a primary output stage of the driver, and are temporarily activated responsive to a transition in an input signal to the driver to effectively decrease the output impedance and boost the pull-up and pull-down time response characteristics of the driver during the transition of the output. The additional output stages are active only for a small part of a cycle, so the slew rate is thereby increased while the effective output impedance during most of the cycle is essentially unaffected.

Abstract: An IO driver utilizes a slew rate boost circuit coupled to an IO driver circuit to improve the slew rate of the driver during transitions on the output of the driver. One or more additional output stages are coupled in parallel with a primary output stage of the driver, and are temporarily activated responsive to a transition in an input signal to the driver to effectively decrease the output impedance and boost the pull-up and pull-down time response characteristics of the driver during the transition of the output. The additional output stages are active only for a small part of a cycle, so the slew rate is thereby increased while the effective output impedance during most of the cycle is essentially unaffected.

Abstract: A design for a high speed differential voltage level shifter circuit arrangement utilizes both PFETs and NFETs controlled by inputs to determine the state of the outputs, which minimizes or eliminates contention on internal nodes when switching from one state to another. As a result, the design minimizes the adverse affects of mismatched NFET and PFET device strengths, and facilitates usage at high frequencies and for level shifting to a range of output voltage levels. The design is also adaptable for use in level shifting to higher or lower output voltages.

Abstract: A design for a high speed differential voltage level shifter circuit arrangement utilizes both PFETs and NFETs controlled by inputs to determine the state of the outputs, which minimizes or eliminates contention on internal nodes when switching from one state to another. As a result, the design minimizes the adverse affects of mismatched NFET and PFET device strengths, and facilitates usage at high frequencies and for level shifting to a range of output voltage levels. The design is also adaptable for use in level shifting to higher or lower output voltages.

Abstract: A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes an L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in the L2 latch during a second half clock cycle. A path opposite a latched data state is gated off in both the L1 latch and the L2 latch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.

Abstract: An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for receiving and processing the data signal, which comprises data represented by a series of voltage state transitions, and pull-up and pull-down array calibration words, for generating and outputting a processed I/O output signal to the resistive element to output a substantially flat v/i response at switching of the data signal.

Abstract: A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes any L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in the L2 latch during a second half clock cycle. A path opposite a latched data state is gated off in both the L1 latch and the L2 latch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.

Abstract: A voltage translator with data buffer includes an input inverter receiving a data input signal at a first voltage level. A level shifting cross-coupled NOR circuit is coupled to the input inverter for translating the data input signal at a second voltage level. An output stage driven by the level shifting cross-coupled NOR circuit for providing a data output signal at the second voltage level. The voltage translator enables improved performance across various power, voltage and temperature (PVT) conditions and reliably reduces or minimizes shoot through current and delay.

Abstract: A decoupling capacitor includes a fixed resistance in series with the capacitor, the resistance formed by contacts connecting a polysilicon layer to metal and a diffusion layer to metal; the contacts being of location and quantity sufficient for limiting defect current while allowing the capacitor to function at high frequency. N pairs of contacts in at least two sets of contacts are separated by a distance K sufficient to achieve a leakage limiting resistance of R and a bandwidth limiting resistance of R/2.

Abstract: A data storage element for use in LSSD compliant circuit designs. The data storage element has an alternate, or scan, data input circuit that has increased immunity to electrical noise while maintaining lower power consumption than the circuits used for primary data input. This increased noise immunity reduces the probably that noise on the alternate data input will cause an unintended change of data state stored in the data storage element. Modification of latch circuits used in the data storage element allow a reduction in the number of transistors used in the latch circuits, thereby compensating for the increase in transistors used in the alternate data input circuit and allowing the data storage element to use the same number of transistors as prior designs that have less noise immunity on their alternate data inputs.