Abstract: A bias device that modifies the bias of a device based on an input signal to the device. The device may have a fixed bias, and the bias device can be connected in parallel with the fixed bias. The device can be an amplifier, such as a linear amplifier or a class AB amplifier. The bias device can be configured to provide maximum bias during the device's crossover time period.

Abstract: The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).

Abstract: The present invention relates to a reverse bias protection structure which comprises a PMOS transistor structure having a drain portion, a gate portion, a source portion and a backgate portion, wherein the gate portion is coupled to a first voltage potential, the source portion is selectively coupleable to a power supply, and the drain portion is selectively coupleable to a circuit needing power to be supplied thereto from the power supply. The reverse bias protection structure further comprises a Schottky diode structure having an anode coupled to the source portion of the PMOS transistor structure, and a cathode coupled to the backgate portion of the PMOS structure. Under forward bias conditions, the PMOS transistor conducts and exhibits a small voltage drop thereacross. Under reverse bias conditions, the PMOS transistor is off and the Schottky structure is reverse biased, thus preventing current through the protection structure.

Abstract: The present invention relates to a motor drive system which comprises a fan controller circuit operable to generate a PWM control signal for control of a motor speed. The fan controller circuit comprises a current detection circuit and a motor speed determination circuit. The system further comprises a fan driver circuit operable to drive a motor at a duty cycle based on the PWM control signal from the fan controller circuit. The fan driver circuit comprises a current sink circuit operable to draw current from the PWM control signal when the PWM control signal is high and when the motor reaches a predetermined position. In the addition, the current detection circuit is operable to detect the current draw on the PWM control signal and provide an indication signal to the fan speed determination circuit associated with such detection. Further, the motor speed determination circuit is operable to determine the speed of the motor based upon a timing associated with successive current draw detections.

Abstract: The present invention relates to a motor drive system which comprises a fan controller circuit operable to generate a PWM control signal for control of a motor speed. The fan controller circuit comprises a current detection circuit and a motor speed determination circuit. The system further comprises a fan driver circuit operable to drive a motor at a duty cycle based on the PWM control signal from the fan controller circuit. The fan driver circuit comprises a current sink circuit operable to draw current from the PWM control signal when the PWM control signal is high and when the motor reaches a predetermined position. In the addition, the current detection circuit is operable to detect the current draw on the PWM control signal and provide an indication signal to the fan speed determination circuit associated with such detection. Further, the motor speed determination circuit is operable to determine the speed of the motor based upon a timing associated with successive current draw detections.

Abstract: The present invention relates to a reverse bias protection structure which comprises a PMOS transistor structure having a drain portion, a gate portion, a source portion and a backgate portion, wherein the gate portion is coupled to a first voltage potential, the source portion is selectively coupleable to a power supply, and the drain portion is selectively coupleable to a circuit needing power to be supplied thereto from the power supply. The reverse bias protection structure further comprises a Schottky diode structure having an anode coupled to the source portion of the PMOS transistor structure, and a cathode coupled to the backgate portion of the PMOS structure. Under forward bias conditions, the PMOS transistor conducts and exhibits a small voltage drop thereacross. Under reverse bias conditions, the PMOS transistor is off and the Schottky structure is reverse biased, thus preventing current through the protection structure.

Abstract: A method of fabricating a bond and the bond. The process includes providing a lower level (M1,13, 15) of electrically conductive metal disposed on a substrate having a pair of spaced apart sections. An electrically insulating layer (11) is then disposed over the lower level and vias (23) are formed in the electrically insulating layer, individual ones of the vias extending to one of the spaced apart section of the lower level. An upper level of electrically conductive metal (M2, 17, 19) is disposed on the electrically insulating layer, the upper level having a pair of spaced apart sections, each coupled to one of the sections of the lower level through a via. One of the pair of spaced apart sections of the lower level is preferably essentially U-shaped (13) and the other section (15) of the lower level is essentially rectangular shaped and extends into the open end of the "U".