Abstract: A method for transmitting data on a bus having multiple data lines is disclosed. Each of the data lines within the bus is assigned a unique binary value. During data transmissions, only one of the data lines within the bus is activated at a time, and each activation of one of the data lines represents its associated unique binary value. Thus, an aggregate of consecutive activations represents the same information as if the data were transmitted in parallel.

Abstract: A method for interconnecting components within a data processing system is disclosed. A number of components is connected to an uni-directional bus. The uni-directional bus is arranged in a loop configuration. Each component has at least one node identification. Communications among these components are provided in the form of messages via a respective node identification. Each message includes a node identification field and a content field.

Abstract: A method for compressing data within a data processing system is disclosed. Each unit of data is at least two bytes. As each byte from a data stream is received, a determination is made as to whether or not an identical data byte occurs at a pre-selected interval within a group of bytes already received. In response to a determination that an identical data byte occurs at a pre-selected interval within a group of bytes already received, only a portion of a subsequent unit of data from the data stream is passed to an output.

Abstract: An apparatus for improving I/O pin interfaces for serial data communications is disclosed. In accordance with a preferred embodiment of the present invention, an improved serial interface is provided, which comprises an oscillator input, a signal input, a counter, a register, and a data output. The counter is utilized to count the number of cycles of the oscillator input for which the signal input is asserted. The register is utilized to receive a value from the counter when the signal input is next de-asserted. The data output is at a first logical state when the signal input is asserted for fewer oscillation cycles than the value stored in the register and the data output is at a second logical state otherwise, such that only one I/O pin is required for serial communications.

Abstract: A method for encoding an input data stream of source symbols to produce an output sequence of pointers is disclosed. An initial part of the input data stream is encoded as a LITERAL.sub.-- POINTER by a compressor. A LITERAL.sub.-- POINTER includes at least one data byte from the data stream. A subsequent part of the input data stream is encoded as a COPY.sub.-- POINTER. The COPY.sub.-- POINTER includes a count and a displacement pointing to a history-buffer within the compressor. All succeeding data bytes from the input data stream are encoded as LITERAL.sub.-- POINTERs and COPY.sub.-- POINTERs in an alternating fashion, such that an encoded output sequence output by the compressor includes a string of pointers alternating between LITERAL.sub.-- POINTERs and COPY.sub.-- POINTERs.

Abstract: A method for encoding an input data stream of source symbols to produce an output sequence of pointers is disclosed. A LITERAL string in an input data stream is first loaded into a history-buffer. A value of a history-buffer pointer is copied to a register to indicate a starting position of the LITERAL string within the history-buffer. A counter is incremented for each subsequent LITERAL symbol from the input data stream. Then, the LITERAL string and each subsequent LITERAL symbol from the input data stream is encoded utilizing a value within the register and a value within the counter as a LITERAL.sub.-- POINTER. Finally, the LITERAL.sub.-- POINTER is outputted from a data compressor.

Abstract: A system and related architecture for providing random access cache storage between a processor accessing data at high speed and in small block units and a mass storage medium holding data in large transfer units. Lossless data compression is applied to large transfer units of data before storage in a DRAM. Cache address space is assigned in allocation units which are assigned without a prespecified pattern within the DRAM but linked through chains. The chain lengths are adjusted to match the compressibility characteristics of transfer units and include resources for scavenging residuals. Logical blocks materially smaller than the transfer units are accessed and decompressed during readout from the DRAM. The system architecture provides resources for accessing the individual logical blocks through an index. The invention is particularly suited for a disk drive cache system having a small cache DRAM in conjunction with a magnetic or optical disk mass storage system reading highly compressible data.

Abstract: A method for providing improved data compression efficiency to a data compressor unit is disclosed. Before sending the uncompressed data stream to the data compressor unit, an incoming data byte from the uncompressed data stream is first compared with a preceding data byte from the uncompressed data stream. A first counter value is incremented in response to a match between the incoming data byte and the preceding data byte. A second counter value is then incremented in response to subsequent matches between an incoming data byte and its preceding data byte after the first counter value has reached a preset value. The second counter value is finally sent to the data compressor unit at the completion of a run of the incoming data byte in substitution of a portion of the run, such that the data compressor unit can quickly resume its optimal compression ratio after an occurrence of the run within the uncompressed data stream.

Abstract: A method for compressing a set of compiled microcode to be utilized within a data processing system is disclosed. In accordance with the method and system of the present invention, all branch instructions within a set of compiled microcode are first identified. Then, the set of compiled microcode is parsed into a number of microcode segments such that each microcode segment begins at an instruction following each identified branch instruction or at a target address of each identified branch instruction. Subsequently, each of these microcode segments is individually translated to its compressed form by utilizing a data-compression routine. Finally, all the compressed microcode segments are concatenated together and linked by inserting branch instructions with modified target address, to yield a set of compressed executable microcode. By doing so, the required memory for storing the compressed executable microcode is reduced.

Abstract: A method for compressing a set of microcode to be utilized within a data processing system is disclosed. In accordance with the method and system of the present invention, a set of compiled microcode is parsed into multiple microcode segments, wherein each of these microcode segments is of equal length. Each of the microcode segments is then individually compressed by utilizing a data-compression routine. Next, all of these compressed microcode segments are concatenated to yield a set of compressed executable microcode. Finally, the starting address for each of the compressed microcode segments is stored in an indexer. By so doing, the required memory for storing the compressed executable microcode is reduced.

Abstract: A generalized data decompression engine is incorporated within a field programmable gate array ("FPGA"). The generalized data decompression engine uses a general purpose data decompression technique such as, for example, a Lempel-Ziv type technique. During operation, a compressed configuration bit stream is received by the generalized data decompression engine in the FPGA and is decompressed thereby. A resultant decompressed configuration bit stream is then used to program logic cells within the FPGA.

Abstract: A data compression apparatus including a circuit for receiving a data element, a storage circuit for sequentially storing previously received data elements at sequentially addressed fixed locations, a circuit for comparing the received data element to the stored data elements to determine whether the received data element matches at least one of the stored data elements, and a circuit for generating an address of the matching stored data element. In addition, a method of compressing data including the steps of receiving a data element, sequentially storing previously received data elements at sequentially addressed fixed locations, comparing the received data element to the stored data elements to determine whether the received data element matches at least one of the stored data elements, and generating an address of the matching stored data element.