Abstract: A frequency locked loop for providing an output signal having an output frequency within a predetermined range of a non-integer multiple of a reference frequency. The frequency locked loop includes a voltage element, such as a voltage controlled oscillator, which produces the output signal at the output frequency. The frequency locked loop further includes a fractional divider which is operably coupled to the voltage controlled oscillator. Further, the frequency locked loop includes a frequency detector, such as a rotational frequency detector, which is operably coupled to the fractional divider. The frequency detector receives the reference signal, such as a fixed clock signal, and the output of the fractional divider signal and outputs a frequency detector signal. In one embodiment, the rotational frequency detector responds to cycle slips of 2&pgr; radians between the reference frequency and the output signal of the fractional divider.