Abstract: A system for testing a digital counter of mn stages, in which the counter is organized into m segments, each of n bits, includes a two input exclusive OR gate connected between each of the m segments. One of the two inputs of each exclusive OR gate is obtained from the carry output of a lower order one of the m segments, and the output of each exclusive OR gate is connected to the carry input of the next higher order one of the m segments. The other inputs to the exclusive OR gates are obtained from a test signal enable input, which is driven high (binary "1") for the test mode of operation. The counter is fully exercised in the test mode in a parallel operation, with full testing of the carry bits from one segment to the next, without any interruption in the clock signal input stream.