Abstract: To provide trimmable inductor structure for a multichip module, direct-chip-attach or surface mount assembly in which an inductive element is formed on or near a surface of the assembly, a planar chip of dielectric or ferrite material is mounted over the inductive element, this chip having on its upper surface a trimmable metallization layer, which may for example be patterned in concentric rings or in a spiral.

Abstract: A testing apparatus for testing integrated circuits at the bare die stage includes a testing station at which microbumps of conductive material are located on interconnection trace terminations of a multilayer interconnection structure, these terminations being distributed in a pattern corresponding to the pattern of contact pads on the die to be tested. To facilitate testing of the die before separation from a wafer using the microbumps, the other connections provided to and from the interconnection structure have a low profile.

Abstract: A test probe structure for making connections to a bare integrated circuit device or a wafer to be tested comprises a multilayer printed circuit probe arm which carries at its tip an MCM-D type substrate having a row of microbumps on its underside to make the required connections. The probe arm is supported at a shallow angle to the surface of the device or wafer, and the MCM-D type substrate is formed with the necessary passive components to interface with the device under test. Four such probe arms may be provided, one on each side of the device under test.

Abstract: In a multichip module structure comprising a silicon, alumina or sapphire substrate carrying a plurality of layers of metallisation separated by polymer dielectric layers, with one or more inductors formed in the uppermost metallisation layer, a ferrite core for one of those inductors is located over the inductor and secured in position by flip chip solder bonding.

Abstract: A ball grid array arrangement comprises a dielectric multilayer substrate, in a lower metallization layer of which is disposed an array of solder balls. A passive circuit element is integrated into at least one of the metallization layers. The arrangement may be either a discrete component consisting of a triplate transmission-line resonator or interdigitated filter integrated into an inner metallization layer and defined by that layer in conjunction with adjacent layers, or it may take the form of an IC carrier or multichip-module carrier having such transmission structures situated within a central die-attach area of the substrate and having also a peripheral area containing bonding structures for the mounting of at least one chip or chip module. There will normally be at least two groups of such bonding structures, and a passive circuit element in the form of an inductor may be formed in the upper metallization layer between adjacent groups of bonding structures.

Abstract: An electrical contact material which consists of a mixture of silver, 5 to 50 weight per cent of copper and 2 to 20 weight per cent of lanthanum, strontium chromite of formula La.sub.1-x Sr.sub.x CrO.sub.3, where the values of x lie between 0 and 1.0, formed as a hard, chemically inert, non-metallic phase of high electrical conductivity both within the bulk of, and at the surface of, the contact material. Methods of producing the electrical contact materials utilizing powder metallurgical techniques are outlined.