Patents by Inventor David John Seibert

David John Seibert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220318475
    Abstract: A system expands an existing library based on simultaneous optimization of a circuit design being built and the library cells being used. The system receives a library of cells and a circuit design and performs synthesis and optimization of the circuit design. The system evaluates the circuit design to identify portions that may be candidates for new library cells. The system analyzes the library to determine whether there is an existing library cell that can be used, whether the new libcell should be added to the library, or whether the new libcell should replace an existing libcell. The system performs modeling for the new libcell to measure the improvement obtained by use of the new libcell. The system recommends the new libcell for addition to the library based on the performance modeling.
    Type: Application
    Filed: March 25, 2022
    Publication date: October 6, 2022
    Inventors: Van Edward Morgan, David John Seibert, Maurizio Damiani, Abhijeet Chakraborty, Tsuwei Ku, Mohammad Ziaullah Khan
  • Patent number: 10360341
    Abstract: Systems and techniques are described for optimizing an integrated circuit (IC) design. Before routing is performed on the IC design in an IC design flow, an IC design tool can iteratively perform a set of operations, the set of operations comprising: (1) modifying a net in the IC design to obtain a modified net, (2) determining a metal layer for routing the modified net, (3) computing a resistance value and a capacitance value of the modified net based on the metal layer, and (4) computing a delay value for the modified net based on the resistance value and the capacitance value.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 23, 2019
    Assignee: Synopsys, Inc.
    Inventors: Abhijeet Chakraborty, David John Seibert, Pingkan Fok, Ramoji Karumuri Rao
  • Publication number: 20190065656
    Abstract: Systems and techniques are described for optimizing an integrated circuit (IC) design. Before routing is performed on the IC design in an IC design flow, an IC design tool can iteratively perform a set of operations, the set of operations comprising: (1) modifying a net in the IC design to obtain a modified net, (2) determining a metal layer for routing the modified net, (3) computing a resistance value and a capacitance value of the modified net based on the metal layer, and (4) computing a delay value for the modified net based on the resistance value and the capacitance value.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Applicant: Synopsys, Inc.
    Inventors: Abhijeet Chakraborty, David John Seibert, Pingkan Fok, Ramoji Karumuri Rao