Patents by Inventor David John Simpson
David John Simpson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934308Abstract: Techniques for data manipulation using processor cluster address generation are disclosed. One or more processor clusters capable of executing software-initiated work requests are accessed. A plurality of dimensions from a tensor is flattened into a single dimension. A work request address field is parsed, where the address field contains unique address space descriptors for each of the plurality of dimensions, along with a common address space descriptor. A direct memory access (DMA) engine coupled to the one or more processor clusters is configured. Addresses are generated based on the unique address space descriptors and the common address space descriptor. The plurality of dimensions can be summed to generate a single address. Memory is accessed using two or more of the addresses that were generated. The addresses are used to enable DMA access.Type: GrantFiled: September 29, 2020Date of Patent: March 19, 2024Inventors: David John Simpson, Stephen Curtis Johnson, Richard Douglas Trauben
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Publication number: 20240061704Abstract: Techniques for data manipulation using processor graph execution using interrupt conservation are disclosed. Processing elements are configured to implement a data flow graph. The processing elements comprise a multilayer graph execution engine. A data engine is loaded with computational parameters for the multilayer graph execution engine. The data engine is coupled to the multilayer graph execution engine, and the computational parameters supply layer-by-layer execution data to the multilayer graph execution engine for data flow graph execution. A first command FIFO is used for loading the data engine with computational parameters, and a second command FIFO is used for loading the multilayer graph execution engine with layer definition data. An input image is provided for a first layer of the multilayer graph execution engine. The data flow graph is executed using the input image and the computational parameters.Type: ApplicationFiled: October 31, 2023Publication date: February 22, 2024Inventor: David John Simpson
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Patent number: 11880426Abstract: Techniques for data manipulation using integer matrix multiplication using pipelining are disclosed. A first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n are obtained for matrix multiplication within a processor. The first and second integer matrices employ a two's complement variable radix point data representation. The first and second integer matrices are distilled into (j×j) submatrices. A first variable radix point format and an initial value for an accumulator register are configured dynamically. A first variable radix point format is configured dynamically for the first integer matrix and a second variable radix point format is configured dynamically for the second integer matrix. Multiply-accumulate operations are executed in a pipelined fashion on the (j×j) submatrices of the first integer matrix and the second integer matrix, where a third variable radix point format is configured for the result.Type: GrantFiled: July 31, 2022Date of Patent: January 23, 2024Inventor: David John Simpson
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Patent number: 11836518Abstract: Techniques for data manipulation using processor graph execution using interrupt conservation are disclosed. Processing elements are configured to implement a data flow graph. The processing elements comprise a multilayer graph execution engine. A data engine is loaded with computational parameters for the multilayer graph execution engine. The data engine is coupled to the multilayer graph execution engine, and the computational parameters supply layer-by-layer execution data to the multilayer graph execution engine for data flow graph execution. A first command FIFO is used for loading the data engine with computational parameters, and a second command FIFO is used for loading the multilayer graph execution engine with layer definition data. An input image is provided for a first layer of the multilayer graph execution engine. The data flow graph is executed using the input image and the computational parameters.Type: GrantFiled: December 10, 2021Date of Patent: December 5, 2023Inventor: David John Simpson
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Publication number: 20220366010Abstract: Techniques for data manipulation using integer matrix multiplication using pipelining are disclosed. A first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n are obtained for matrix multiplication within a processor. The first and second integer matrices employ a two's complement variable radix point data representation. The first and second integer matrices are distilled into (j×j) submatrices. A first variable radix point format and an initial value for an accumulator register are configured dynamically. A first variable radix point format is configured dynamically for the first integer matrix and a second variable radix point format is configured dynamically for the second integer matrix. Multiply-accumulate operations are executed in a pipelined fashion on the (j×j) submatrices of the first integer matrix and the second integer matrix, where a third variable radix point format is configured for the result.Type: ApplicationFiled: July 31, 2022Publication date: November 17, 2022Inventor: David John Simpson
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Patent number: 11481472Abstract: Techniques for data manipulation using integer matrix multiplication using pipelining are disclosed. A first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n are obtained for matrix multiplication within a processor. The first and second integer matrices employ a two's complement variable radix point data representation. The first and second integer matrices are distilled into (j×j) submatrices. A first variable radix point format and an initial value for an accumulator register are configured dynamically. A first variable radix point format is configured dynamically for the first integer matrix and a second variable radix point format is configured dynamically for the second integer matrix. Multiply-accumulate operations are executed in a pipelined fashion on the (j×j) submatrices of the first integer matrix and the second integer matrix, where a third variable radix point format is configured for the result.Type: GrantFiled: July 30, 2020Date of Patent: October 25, 2022Inventor: David John Simpson
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Publication number: 20220197692Abstract: Techniques for data manipulation using processor graph execution using interrupt conservation are disclosed. Processing elements are configured to implement a data flow graph. The processing elements comprise a multilayer graph execution engine. A data engine is loaded with computational parameters for the multilayer graph execution engine. The data engine is coupled to the multilayer graph execution engine, and the computational parameters supply layer-by-layer execution data to the multilayer graph execution engine for data flow graph execution. A first command FIFO is used for loading the data engine with computational parameters, and a second command FIFO is used for loading the multilayer graph execution engine with layer definition data. An input image is provided for a first layer of the multilayer graph execution engine. The data flow graph is executed using the input image and the computational parameters.Type: ApplicationFiled: December 10, 2021Publication date: June 23, 2022Inventor: David John Simpson
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Patent number: 11227030Abstract: Techniques for data manipulation using a matrix multiplication engine using pipelining are disclosed. A first and a second matrix are obtained for matrix multiplication. A first matrix multiply-accumulate (MAC) unit is configured, where a first matrix element and a second matrix element are presented to the MAC unit on a first cycle. A second MAC unit is configured in pipelined fashion, where the first element of the first matrix and a second element of the second matrix are presented to the second MAC unit on a second cycle, and where a second element of the first matrix and the first element of the second matrix are presented to the first MAC unit on the second cycle. Additional MAC units are further configured within the processor in pipelined fashion. Multiply-accumulate operations are executed in pipelined fashion on each of n MAC units over additional k sets of m cycles.Type: GrantFiled: March 31, 2020Date of Patent: January 18, 2022Assignee: Wave Computing, Inc.Inventor: David John Simpson
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Patent number: 10997102Abstract: Techniques for data manipulation using processor cluster address generation are disclosed. One or more processor clusters capable of executing software-initiated work requests are accessed. A direct memory access (DMA) engine, coupled to the one or more processor clusters, is configured, wherein the DMA engine employs address generation across a plurality of tensor dimensions. A work request address field is parsed, where the address field contains unique address space descriptors for each of the plurality of dimensions, along with a common address space descriptor. DMA addresses are generated based on the unique address space descriptors and the common address space descriptor. Memory using two or more of the DMA addresses that were generated is accessed, where the two or more DMA addresses enable processing within the one or more processor clusters.Type: GrantFiled: August 12, 2020Date of Patent: May 4, 2021Assignee: Wave Computing, Inc.Inventors: David John Simpson, Richard Douglas Trauben, Stephen Curtis Johnson
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Publication number: 20210011849Abstract: Techniques for data manipulation using processor cluster address generation are disclosed. One or more processor clusters capable of executing software-initiated work requests are accessed. A plurality of dimensions from a tensor is flattened into a single dimension. A work request address field is parsed, where the address field contains unique address space descriptors for each of the plurality of dimensions, along with a common address space descriptor. A direct memory access (DMA) engine coupled to the one or more processor clusters is configured. Addresses are generated based on the unique address space descriptors and the common address space descriptor. The plurality of dimensions can be summed to generate a single address. Memory is accessed using two or more of the addresses that were generated. The addresses are used to enable DMA access.Type: ApplicationFiled: September 29, 2020Publication date: January 14, 2021Inventors: David John Simpson, Stephen Curtis Johnson, Richard Douglas Trauben
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Publication number: 20200387564Abstract: Techniques for data manipulation using integer matrix multiplication using pipelining are disclosed. A first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n are obtained for matrix multiplication within a processor. The first and second integer matrices employ a two's complement variable radix point data representation. The first and second integer matrices are distilled into (j×j) submatrices. A first variable radix point format and an initial value for an accumulator register are configured dynamically. A first variable radix point format is configured dynamically for the first integer matrix and a second variable radix point format is configured dynamically for the second integer matrix. Multiply-accumulate operations are executed in a pipelined fashion on the (j×j) submatrices of the first integer matrix and the second integer matrix, where a third variable radix point format is configured for the result.Type: ApplicationFiled: July 30, 2020Publication date: December 10, 2020Inventor: David John Simpson
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Publication number: 20200371978Abstract: Techniques for data manipulation using processor cluster address generation are disclosed. One or more processor clusters capable of executing software-initiated work requests are accessed. A direct memory access (DMA) engine, coupled to the one or more processor clusters, is configured, wherein the DMA engine employs address generation across a plurality of tensor dimensions. A work request address field is parsed, where the address field contains unique address space descriptors for each of the plurality of dimensions, along with a common address space descriptor. DMA addresses are generated based on the unique address space descriptors and the common address space descriptor. Memory using two or more of the DMA addresses that were generated is accessed, where the two or more DMA addresses enable processing within the one or more processor clusters.Type: ApplicationFiled: August 12, 2020Publication date: November 26, 2020Inventors: David John Simpson, Richard Douglas Trauben, Stephen Curtis Johnson
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Publication number: 20200311183Abstract: Techniques for data manipulation using a matrix multiplication engine using pipelining are disclosed. A first and a second matrix are obtained for matrix multiplication. A first matrix multiply-accumulate (MAC) unit is configured, where a first matrix element and a second matrix element are presented to the MAC unit on a first cycle. A second MAC unit is configured in pipelined fashion, where the first element of the first matrix and a second element of the second matrix are presented to the second MAC unit on a second cycle, and where a second element of the first matrix and the first element of the second matrix are presented to the first MAC unit on the second cycle. Additional MAC units are further configured within the processor in pipelined fashion. Multiply-accumulate operations are executed in pipelined fashion on each of n MAC units over additional k sets of m cycles.Type: ApplicationFiled: March 31, 2020Publication date: October 1, 2020Inventor: David John Simpson
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Patent number: 8166350Abstract: A computer-readable medium is configured to receive a report processing request at a hierarchical report processor. The hierarchical report processor includes a parent process and at least one child process executing on a single processing unit, and is configured to process the report processing request as a task on the single processing unit.Type: GrantFiled: March 5, 2010Date of Patent: April 24, 2012Assignee: Business Objects Software Ltd.Inventors: David John Simpson, Philipp Ziegler
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Publication number: 20100162254Abstract: A computer-readable medium is configured to receive a report processing request at a hierarchical report processor. The hierarchical report processor includes a parent process and at least one child process executing on a single processing unit, and is configured to process the report processing request as a task on the single processing unit.Type: ApplicationFiled: March 5, 2010Publication date: June 24, 2010Inventors: David John Simpson, Philipp Ziegler
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Patent number: 7681087Abstract: A computer-readable medium is configured to receive a report processing request at a hierarchical report processor. The hierarchical report processor includes a parent process and at least one child process executing on a single processing unit, and is configured to process the report processing request as a task on the single processing unit.Type: GrantFiled: December 14, 2005Date of Patent: March 16, 2010Assignee: Business Objects Software Ltd.Inventors: David John Simpson, Philipp Ziegler
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Publication number: 20100015107Abstract: The invention relates to genetic elements capable of improving the levels of expression of operably-linked transcription units. In particular, said genetic elements are derived from the 5? untranslated regions of ribosomal protein genes and may comprise a CpG island. Also provided are vectors and host cells comprising said genetic elements and methods of use to obtain high levels of recombinant gene expression.Type: ApplicationFiled: September 9, 2009Publication date: January 21, 2010Applicant: Millipore CorporationInventors: David John Simpson, Steven Geraint Williams, Alistair Simpson Irvine
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Patent number: 7632661Abstract: The invention relates to genetic elements capable of improving the levels of expression of operably-linked transcription units. In particular, said genetic elements are derived from the 5? untranslated regions of ribosomal protein genes and may comprise a CpG island. Also provided are vectors and host cells comprising said genetic elements and methods of use to obtain high levels of recombinant gene expression.Type: GrantFiled: May 17, 2006Date of Patent: December 15, 2009Assignee: Millipore CorporationInventors: David John Simpson, Steven Geraint Williams, Alistair Simpson Irvine
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Publication number: 20080097088Abstract: The invention relates to genetic elements capable of improving the levels of expression of operably-linked transcription units. In particular, said genetic elements are derived from the 5? untranslated regions of ribosomal protein genes and may comprise a CpG island. Also provided are vectors and host cells comprising said genetic elements and methods of use to obtain high levels of recombinant gene expression.Type: ApplicationFiled: May 17, 2006Publication date: April 24, 2008Inventors: David John Simpson, Steven Geraint Williams, Alistair Simpson Irvine
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Publication number: 20080082707Abstract: A method and apparatus is disclosed herein for a bus controller that supports a flexible bus protocol that handles pipelined, variable latency bus transactions while maintaining point-to-point (P2P) FIFO ordering of transactions in a non-blocking manner. In one embodiment, the apparatus includes a bus controller to receive a plurality of bus transactions at a first incoming port from a bus. The bus controller is configured to process the plurality of bus transactions in a pipelined manner, maintaining P2P FIFO ordering of the plurality of bus transactions even when the plurality of bus transactions take a variable number of cycles to complete.Type: ApplicationFiled: September 28, 2007Publication date: April 3, 2008Inventors: Shail Aditya Gupta, David John Simpson