Abstract: A signal used in the transmission of data in a communication system (for example in an ATM network), comprised of immediately successive cells. For the purpose of cell synchronization, filler cells (I) containing a predefined bit pattern are provided. This pattern is provided with an error protection code that differs from the error protection code used for the user data. Even if the user data should coincidentally contain the predefined bit pattern, the synchronization circuit will not be able to be simulated, since this false bit pattern is provided with a different error protection code. In order to test and ensure the synchronization state, a BIP value at the end of the cell is checked at the receiver end.

Abstract: A signal used in the transmission of data in a communication system (for example in an ATM network), comprised of immediately successive cells. For the purpose of cell synchronization, filler cells (I) containing a predefined bit pattern are provided. This pattern is provided with an error protection code that differs from the error protection code used for the user data. Even if the user data should coincidentally contain the predefined bit pattern, the synchronization circuit will not be able to be simulated, since this false bit pattern is provided with a different error protection code. In order to test and ensure the synchronization state, a BIP value at the end of the cell is checked at the receiver end.

Abstract: A signal used in the transmission of data in a communication system including immediately successive cells for the purpose of cell synchronization, includes filler cells containing a predefined bit pattern. This pattern is provided with an error protection code that differs from an error protection code used for user data. Even if the user data should coincidentally contain the predefined bit pattern, the synchronization circuit will not be able to be simulated, since this false bit pattern is provided with a different error protection code. In order to test and ensure the synchronization state, a BIP (bit interleaved parity) value at the end of the cell is checked at the receiver end.

Abstract: A slave clock generation system and method suitable for use with synchronous telecommunications networks generates one or more slave clocks from a selected reference clock using a direct digital synthesis technique. A multiplexer selects a reference clock from a number of available sources, each of which can be at its own spot frequency, based on a predetermined selection order. Toggle detectors monitor each of the available clock sources, and block the selection of any that are not within a specified frequency range. A local oscillator establishes short-term and long-term measurement periods; the cycles of the selected reference clock are counted over consecutive short-term measurement periods to determine the relative frequency of the selected clock with respect to the frequency of the local oscillator. The cycle counts are fed to a phase-to-clock converter, which produces a slave clock output having a frequency that varies with the relative frequency measured for the selected clock.

Abstract: Four parallel lines are provided for the guided transmission of a data flow with a high rate (sub-GHz range). Two data bits per transmission clock are transmitted via these lines. The other two remaining lines are used for signaling certain changes in both data bits. Data transmission and signaling are accomplished on the basis of the Grey code. In other words, only one of the four lines changes state per clock. The interface according to the invention has reduced sensitivity to signal skew and permits simple clock recovery in terms of circuit engineering.