Abstract: A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C-SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000° C., to a thickness of at least 0.5?. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.

Abstract: A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C-SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000 ° C., to a thickness of at least 0.5?. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.

Abstract: A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C—SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000° C., to a thickness of at least 0.5 ?m. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.

Abstract: A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C—SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000° C., to a thickness of at least 0.5 ?m. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.

Abstract: The invention relates to a method of fabricating a semiconductor device, the method including: providing a stacked semiconductor structure having a substrate, a buffer layer and one or more device layers; depositing a layer of AlSb on one or more regions of the upper surface of the stacked structure; and oxidising the AlSb layer in the presence of water to form a layer of aluminium oxide on the one or more regions of the upper surface. The semiconductor device is preferably a field effect transistor, and the method preferably includes the additional step of depositing source, drain and/or gate electrodes. In preferred embodiments, the method is controlled so as to avoid exposing the intermediate AlSb structure to the atmosphere and/or the oxidation step is conducted at a temperature between 100° and 300° C.

Abstract: A semiconductor device comprises an active layer above a first confinement layer. The active layer comprises a layer of ?-Sn less than 20 nm thick. The first confinement layer is formed of material with a wider band gap than ?-Sn, wherein the band gap offset between ?-Sn and this material allows confinement of charge carriers in the active layer so that the active layer acts as a quantum well. A similar second confinement layer may be formed over the active layer. This semiconductor device may be a p-FET. A method of fabricating such a semiconductor device is described.

Abstract: A semiconductor device comprises the following elements: an active layer comprising a quantum well structure and a buffer layer beneath the active layer adapted to form a confinement layer for charge carriers in the active layer. The buffer layer is adapted so as not to increase an overall strain in the active layer. The active layer is already strained as a result of a lattice mismatch between the active layer and the buffer layer. Strain in the buffer layer may be controlled by use of a strain control buffer layer and by appropriate choices of material and composition for the buffer layer and for a substrate on which the buffer layer is grown.

Abstract: A semiconductor device comprises an active layer above a first confinement layer. The active layer comprises a layer of ?-Sn less than 20 nm thick. The first confinement layer is formed of material with a wider band gap than ?-Sn, wherein the band gap offset between ?-Sn and this material allows confinement of charge carriers in the active layer so that the active layer acts as a quantum well. A similar second confinement layer may be formed over the active layer. This semiconductor device may be a p-FET. A method of fabricating such a semiconductor device is described.

Abstract: A semiconductor device structure comprises an active layer and a buffer layer. The active layer is a quantum well structure. There is a lattice mismatch between the buffer layer and the active layer which places the active layer under biaxial compressive strain. Uniaxial tensile strain is applied to the active layer to reduce compressive strain on the active layer in a second direction but not in a first direction. This favours hole and electron mobility in the first direction, rendering the semiconductor device structure suitable for the formation of both p-channel and n-channel devices.

Abstract: This invention relates to methods of determining physical characteristics of and identifying and locating defects in substrates, such as semiconductor wafers, optical thin films, display screens and the like. The method involve use of PC scanners to image the substrate. In particular PC scanners used in transmission mode imaging allow information about the volume of the substrate to be determined. The method allows determination of characteristics such as layer thickness, curvature and optical constants through use of interferometery techniques and bifrefringence and strain through use of polarised imaging. The methods also relate to stimulating luminescence in the substrate, for example photoluminescence and electroluminescence and scanning the stimulated substrate for luminescence mapping.