Abstract: One or more examples relate, generally, to systems, methods and devices for performing authenticated encryption that provides assurance of the authenticity of data through the encryption and decryption processes.

Abstract: A power-saving method and circuit in a data processing device comprising a data buffer. Data transfer commands associated with a data source and a data destination are received at the data processing device. The data transfer commands are accumulated until an amount of data associated with the read commands is greater than a predefined threshold. When the amount of data is less than the predefined threshold and the data buffer is empty, the data buffer is signaled to enter or to maintain a power saving mode. When the amount of data is at least the predefined threshold, the data buffer is signaled to exit the power saving mode following a predetermined delay. Processing of the commands and data in respective pipelines is monitored to time exiting of the buffer from the power saving mode for arrival of the data. Power saving mode use and thus power saving are optimized.

Abstract: The present disclosure provides a method of scheduling data processing at a pipelined data processing engine, and a command scheduler for scheduling data processing at the pipelined data processing engine. The command scheduler determines whether a first data stream is locked to the pipelined data processing engine based on a status of a current data frame of the first data stream in the pipelined data processing engine. The command scheduler will schedule a next data frame of the first data stream to the data processing engine if the first data stream is not locked to the pipelined data processing engine, or it will postpone the scheduling of the next data frame of the first data stream if the first data stream is locked to the pipelined data processing engine.

Abstract: A method and apparatus for handling SGLs for out of order systems is disclosed. The method involves generating multiple Child IOs from an original IO, each Child IO being at the granularity of a storage side memory; generating separate SG lists for each Child IO; and processing each Child IO independently of other Child IOs and in order with each Child IO for data transfer. As each Child IO is generated at the granularity of the storage side memory, the Child IOs can be processed independently of each other and in-order within each Child IO. Thus, an out-of order IO transfer is transformed into an in-order IO transfer.

Abstract: A power-saving method and circuit in a data processing device comprising a data buffer. Read commands associated with a data source and a data destination are received at the data processing device. The read commands are accumulated until an amount of read data associated with the read commands is greater than a predefined threshold. When the amount of read data is less than the predefined threshold and the data buffer is empty, the data buffer is signaled to enter or to maintain a sleep mode. When the amount of read data is at least the predefined threshold, the data buffer is signaled to exit the sleep mode following a preconfigured delay. Processing of the read commands and read data in respective pipelines is monitored to time exiting of the buffer from the sleep mode for arrival of the read data. Sleep mode use and thus power saving are optimized.

Abstract: A data integrity (DI) protection circuit and method provide overlapping DI protection without increasing memory requirements. Write data parity is checked after write data error correcting code (ECC) check bits are generated, which is stored with the write data in memory without storing the write data parity. A corrupt location cache stores the write address and a write response error is generated when a write data parity error or write address parity error is detected. Read data and read data ECC check bits retrieved from the memory are checked and single bit errors are corrected, while double-bit errors result in a read error response. Read data parity is generated, and the corrected read data and corrected read data ECC check bits are then checked for bit errors. The corrupt location cache is searched for the read address, and a cache hit results in a read error response.

Abstract: A method or system or apparatus provides improved digital communication. In one aspect, destination scheduling is performed by scheduling polling rather than scheduling data emissions. In particular aspects, a loop port scheduler assigns a weight and sequence number to each destination and scheduling polling of ports using these parameters.