Patents by Inventor DAVID JOSEPH HAWKINS

DAVID JOSEPH HAWKINS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220091886
    Abstract: A method and system for an enhanced weighted fair queuing technique for a resource are provided. A plurality of request streams is received at a requestor, each request stream including request messages from a process executing on the requestor. The request messages of each request stream are apportioned to an input queue associated with the request stream; each input queue has a weight. A virtual finish time is determined for each request message based, at least in part, on the weights of the input queues. A sequence of request messages is determined based, at least in part, on the virtual finish times of the request messages. The sequence of request messages is enqueued into an output queue. The sequence of request messages is sent to a resource, over a connection, which provides a service for each process.
    Type: Application
    Filed: September 22, 2020
    Publication date: March 24, 2022
    Applicant: Arm Limited
    Inventors: Michael Andrew Campbell, Peter Owen Hawkins, David Joseph Hawkins
  • Patent number: 11181957
    Abstract: An improved apparatus and method for the protection of reset in systems with stringent safety goals that employ primary and shadow logic blocks with a lock-step checker to achieve functional safety, including those systems having very large fanout of primary and shadow reset signal trees. The disclosed apparatus and method support assertion of reset that is asynchronous to the system clock and deassertion of reset that is synchronous to the system clock. Shadow logic blocks have reset deasserted a fixed number of clock cycles after their respective primary logic blocks, thereby avoiding the requirement to synchronize the primary and shadow reset signal trees at each of their end points to ensure lock-step operation between the primary and shadow logic blocks.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 23, 2021
    Assignee: Arm Limited
    Inventors: Ramamoorthy Guru Prasadh, Tushar P Ringe, Kishore Kumar Jagadeesha, David Joseph Hawkins, Saira Samar Malik
  • Patent number: 10761561
    Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 1, 2020
    Assignee: Arm Limited
    Inventors: Saira Samar Malik, David Joseph Hawkins, Andrew David Tune, Guanghui Geng, Julian Jose Hilgemberg Pontes
  • Patent number: 10713187
    Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 14, 2020
    Assignee: ARM Limited
    Inventors: Michael Filippo, Jamshed Jalal, Klas Magnus Bruce, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava, Joseph Michael Pusdesris
  • Publication number: 20190361486
    Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 28, 2019
    Inventors: Saira Samar MALIK, David Joseph HAWKINS, Andrew David TUNE, Guanghui GENG, Julian Jose Hilgemberg PONTES
  • Publication number: 20190347217
    Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Inventors: Michael FILIPPO, Jamshed JALAL, Klas Magnus BRUCE, Paul Gilbert MEYER, David Joseph HAWKINS, Phanindra Kumar MANNAVA, Joseph Michael PUSDESRIS
  • Patent number: 10402349
    Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: September 3, 2019
    Assignee: ARM Limited
    Inventors: Michael Filippo, Jamshed Jalal, Klas Magnus Bruce, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava, Joseph Michael Pusdesris
  • Patent number: 10402425
    Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: September 3, 2019
    Assignee: Oracle International Corporation
    Inventors: David A. Brown, Rishabh Jain, Michael Duller, Sam Idicula, Erik Schlanger, David Joseph Hawkins, Christopher Joseph Daniels
  • Publication number: 20180329975
    Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.
    Type: Application
    Filed: July 24, 2018
    Publication date: November 15, 2018
    Inventors: DAVID A. BROWN, RISHABH JAIN, MICHAEL DULLER, SAM IDICULA, ERIK SCHLANGER, DAVID JOSEPH HAWKINS, CHRISTOPHER JOSEPH DANIELS
  • Patent number: 10061832
    Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: August 28, 2018
    Assignee: Oracle International Corporation
    Inventors: David A. Brown, Sam Idicula, Erik Schlanger, Rishabh Jain, Michael Duller, Christopher Joseph Daniels, David Joseph Hawkins
  • Patent number: 10061714
    Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: August 28, 2018
    Assignee: Oracle International Corporation
    Inventors: David A. Brown, Rishabh Jain, Michael Duller, Sam Idicula, Erik Schlanger, David Joseph Hawkins
  • Patent number: 10055358
    Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: August 21, 2018
    Assignee: Oracle International Corporation
    Inventors: David A. Brown, Rishabh Jain, Sam Idicula, Erik Schlanger, David Joseph Hawkins
  • Publication number: 20180225232
    Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 9, 2018
    Inventors: Michael FILIPPO, Jamshed JALAL, Klas Magnus BRUCE, Paul Gilbert MEYER, David Joseph HAWKINS, Phanindra Kumar MANNAVA, Joseph Michael PUSDESRIS
  • Publication number: 20180150542
    Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Inventors: DAVID A. BROWN, SAM IDICULA, ERIK SCHLANGER, RISHABH JAIN, MICHAEL DULLER, CHRISTOPHER JOSEPH DANIELS, DAVID JOSEPH HAWKINS
  • Publication number: 20170270053
    Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 21, 2017
    Inventors: DAVID A. BROWN, RISHABH JAIN, SAM IDICULA, ERIK SCHLANGER, DAVID JOSEPH HAWKINS
  • Publication number: 20170270052
    Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 21, 2017
    Inventors: DAVID A. BROWN, RISHABH JAIN, MICHAEL DULLER, SAM IDICULA, ERIK SCHLANGER, DAVID JOSEPH HAWKINS