Abstract: A compression scheme can be selected for an input data stream based on characteristics of the input data stream. For example, when the input data stream is searched for pattern matches, input stream characteristics used to select a compression scheme can include one or more of: type and size of an input stream, a length of a pattern, a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, a gap between two pattern matches (including different or same patterns), standard deviation of a length of a pattern, standard deviation of a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, or standard deviation of a gap between two pattern matches. Criteria can be established whereby one or more characteristics are used to select a particular encoding scheme.

Abstract: Examples described herein relate to an encoder circuitry to apply one of multiple lossless data compression schemes on input data. In some examples, to compress input data, the encoder circuitry is to utilize a search window size and number of searches based on an applied compression scheme. In some examples, content of a memory is reconfigured to store data corresponding to a search window size of the applied compression scheme. In some examples, an applicable hash function is configured based on the applied compression scheme. In some examples, a number of searches are made for a byte position. In some examples, the encoder circuitry includes a hash table look-up and a bank decoder. In some examples, the hash table look-up is to generate a hash index to identify an address of an entry in the search window. In some examples, the bank decoder is to select a bank based on the hash index.

Abstract: In connection with compression of an input stream, multiple portions of the input stream are searched against previously received portions of the input stream to find any matches of character strings in the previously received portions of the input stream. In some cases, matches of longer character strings, as opposed to shorter character strings, can be selected for inclusion in an encoded stream that is to be compressed. Delayed selection can occur whereby among multiple matches, a match that is longer can be selected for inclusion in the encoded stream and non-selected a character string match is reverted to a literal. A search engine that is searching an input stream to identify a repeat pattern of characters can cease to search for characters that were included in the selected character string match.

Abstract: In connection with compression of an input stream, multiple portions of the input stream are searched against previously received portions of the input stream to find any matches of character strings in the previously received portions of the input stream. In some cases, matches of longer character strings, as opposed to shorter character strings, can be selected for inclusion in an encoded stream that is to be compressed. Delayed selection can occur whereby among multiple matches, a match that is longer can be selected for inclusion in the encoded stream and non-selected a character string match is reverted to a literal. A search engine that is searching an input stream to identify a repeat pattern of characters can cease to search for characters that were included in the selected character string match.

Abstract: A compression scheme can be selected for an input data stream based on characteristics of the input data stream. For example, when the input data stream is searched for pattern matches, input stream characteristics used to select a compression scheme can include one or more of: type and size of an input stream, a length of a pattern, a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, a gap between two pattern matches (including different or same patterns), standard deviation of a length of a pattern, standard deviation of a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, or standard deviation of a gap between two pattern matches. Criteria can be established whereby one or more characteristics are used to select a particular encoding scheme.

Abstract: A compression engine includes sets of independent search engines. The sets of independent search engines concurrently perform searches for a longest match in a stream of uncompressed data. The searches are distributed amongst the sets of independent search engines on byte boundaries to load balance the use of the search engines.

Abstract: A multi-threaded processor may support efficient pattern matching techniques. An input data buffer may be provided, which may be shared between a fast path and a slow path. The processor may retire the data units in the input data buffer that is not required and thus avoids copying the data unit used by the slow path. The data management and the execution efficiency may be enhanced as multiple threads may be created to verify potential pattern matches in the input data stream. Also, the threads, which may stall may exit the execution units allowing other threads to run. Further, the problem of state explosion may be avoided by allowing the creation of parallel threads, using the fork instruction, in the slow path.

Abstract: A multi-threaded processor may support efficient pattern matching techniques. An input data buffer may be provided, which may be shared between a fast path and a slow path. The processor may retire the data units in the input data buffer that is not required and thus avoids copying the data unit used by the slow path. The data management and the execution efficiency may be enhanced as multiple threads may be created to verify potential pattern matches in the input data stream. Also, the threads, which may stall may exit the execution units allowing other threads to run. Further, the problem of state explosion may be avoided by allowing the creation of parallel threads, using the fork instruction, in the slow path.

Abstract: A multi-threaded processor may support efficient pattern matching techniques. An input data buffer may be provided, which may be shared between a fast path and a slow path. The processor may retire the data units in the input data buffer that is not required and thus avoids copying the data unit used by the slow path. The data management and the execution efficiency may be enhanced as multiple threads may be created to verify potential pattern matches in the input data stream. Also, the threads, which may stall may exit the execution units allowing other threads to run. Further, the problem of state explosion may be avoided by allowing the creation of parallel threads, using the fork instruction, in the slow path.

Abstract: A multi-threaded processor may support efficient pattern matching techniques. An input data buffer may be provided, which may be shared between a fast path and a slow path. The processor may retire the data units in the input data buffer that is not required and thus avoids copying the data unit used by the slow path. The data management and the execution efficiency may be enhanced as multiple threads may be created to verify potential pattern matches in the input data stream. Also, the threads, which may stall may exit the execution units allowing other threads to run. Further, the problem of state explosion may be avoided by allowing the creation of parallel threads, using the fork instruction, in the slow path.

Abstract: Apparatuses and methods to perform pattern matching are presented. In one embodiment, an apparatus comprises a memory to store a first pattern table comprising information indicative of whether a byte of input data matches a pattern and whether to ignore other matches of the pattern occur in remaining bytes of the input data. The apparatus further comprises one-byte match logic coupled to the memory, to determine, based on the information in the first pattern table, a one-byte match event with respect to the input data. The apparatus further comprises a control unit to filter the other matches of the pattern based on the information of the first pattern table.

Abstract: An embodiment may include circuitry to determine, at least in part, based at least in part upon history information, whether one or more reference patterns are present in a data stream in a packet flow. The data stream may span at least one packet boundary in the packet flow. The history information may include a beginning portion of a packet in the data stream, an ending portion of the packet, and another portion of the data stream. The circuitry may overwrite the another portion of the history information with a respective portion of the data stream to be examined by the circuitry depending, at least in part, upon whether the circuitry determines, at least in part, whether the one or more reference patterns are present in the data stream. The respective portion may be relatively closer than the another portion is to a beginning of the data stream.

Abstract: Apparatuses and methods to perform pattern matching are presented. In one embodiment, an apparatus comprises a memory to store a first pattern table comprising information indicative of whether a byte of input data matches a pattern and whether to ignore other matches of the pattern occur in remaining bytes of the input data. The apparatus further comprises one-byte match logic coupled to the memory, to determine, based on the information in the first pattern table, a one-byte match event with respect to the input data. The apparatus further comprises a control unit to filter the other matches of the pattern based on the information of the first pattern table.

Abstract: A computer system includes a central processing unit (CPU), system read-only memory (ROM), a random access memory (RAM) and a system controller. The system ROM includes a reset vector. A portion of the RAM is used to shadow the system ROM. The system controller is connected between the CPU, the system ROM and the RAM. The system memory includes an internal memory for storing first data. The system memory also includes logic which, in response to receiving an access to a reset vector stored in the system ROM, returns the first data stored in the internal memory.

Abstract: The present invention is directed at prioritizing and interleaving data transfer protocols between storage mediums and main memories. The invention includes a controller interface that is operatively connected to a plurality of storage mediums, a main memory and a central processing unit (CPU). The controller interface is preferably configured to receive and detect data transfer protocol requests having different timing parameters. Once the controller interface receives a data transfer protocol request, an arbitration unit that is operatively coupled to said controller interface assigns priorities to the detected data transfer protocols having different timing parameters. The arbitration unit then compares the assigned priorities, and interrupts an on-going data transfer protocol when a newly received data transfer protocol is assigned a higher priority. The data transfer protocol assigned the high priority is then commenced and proceeds to completion.

Abstract: This is an improved FIFO controller which is capable of buffering data between systems which are asynchronous relative to one another and is free of false flags and internal metastability. The FIFO controller comprises a controller means for receiving read/write data strobes and for generating an initial read/write pointer and a next read/write pointer. Memory means are coupled to the controller means for storing the read/write pointer and read/write data information. Flag generation means are coupled to the controller means for computing a status of the FIFO flags and for preventing momentary false flags.

Abstract: A cache memory system operates without requiring valid bits in the external cache tag RAM by employing a system controller as a writeback cache controller for control of the cache data/tag memory and the system main memory. The system controller receives signaling information from a CPU through a host bus to indicate when to pre-load the cache memory or to flush (disable) the cache memory while maintaining memory coherencey by causing the cache controller to write back all modified lines in the cache memory to the main memory.

Abstract: A computer system is disclosed that permits multiple write buffer read-arounds. The system comprises a CPU (Central Processing Unit) for executing cycles for the computer system, a cache coupled to the CPU for storing data, a write buffer coupled to the CPU for receiving write data from the CPU, an arbiter to control bus accesses to the slave, and processing signals coupled between the cache and the write buffer for permitting the CPU to read-around the write buffer a plurality of times before the write data in the write buffer is flushed therefrom. The processing signals determine when the data stored in the write buffer is also stored in the cache, and, therefore, the cache is permitted to read-around the write buffer more than one time as long as the write buffer has the same data stored therein as exists in the cache.

Abstract: A digital computer system having a "smart" cache controller that permits the system to take advantage of CPU address pipelining while minimizing the performance impact of a pipelined cache read miss in a system with a relatively low hit ratio such as a direct mapped cache.