Abstract: An information handling system includes multiple PCIe devices and a basic input/output system (BIOS). The BIOS receive a system management interrupt (SMI). The SMI is in response to a detection of an error on a first PCIe device of the PCIe devices. The BIOS collect data associated with the first PCIe device. The data includes a friendly full device description for the first PCIe device. Based on the friendly full device description, the BIOS determine a friendly name for the PCIe device. The BIOS provide an error message on a display device of the information handling system. The error message includes a type of the error detected and the friendly name for the PCIe device.

Abstract: An information handling system includes a processor and a basic input/output system (BIOS). The processor executes an operating system, and detects a corrected error from a memory controller of the information handling system. In response, the processor generates a system management interrupt (SMI). In response to the SMI the BIOS executes a SMI handler. The SMI handler detects a row of the corrected error within a dual inline memory module (DIMM) of the information handling system, and determines whether an entry for the row is located within a hash table. In response to the entry for the row being located within the hash table, the SMI handler increments an error count in a field of the entry for the row. Otherwise, the SMI handler adds a new entry for the row to the hash table, and increments an error count in a field of the new entry for the row.

Abstract: An information handling system includes a processor and a basic input/output system (BIOS). The processor executes an operating system, and detects a corrected error from a memory controller of the information handling system. In response, the processor generates a system management interrupt (SMI). In response to the SMI the BIOS executes a SMI handler. The SMI handler detects a row of the corrected error within a dual inline memory module (DIMM) of the information handling system, and determines whether an entry for the row is located within a hash table. In response to the entry for the row being located within the hash table, the SMI handler increments an error count in a field of the entry for the row. Otherwise, the SMI handler adds a new entry for the row to the hash table, and increments an error count in a field of the new entry for the row.

Abstract: An information handling system includes a processor and a basic input/output system (BIOS). The processor executes an operating system, and detects a corrected error from a memory controller of the information handling system. In response, the processor generates a system management interrupt (SMI). In response to the SMI the BIOS executes a SMI handler. The SMI handler detects a row of the corrected error within a dual inline memory module (DIMM) of the information handling system, and determines whether an entry for the row is located within a hash table. In response to the entry for the row being located within the hash table, the SMI handler increments an error count in a field of the entry for the row. Otherwise, the SMI handler adds a new entry for the row to the hash table, and increments an error count in a field of the new entry for the row.

Abstract: An information handling system includes a first memory, a second memory, and a central processor. The first memory includes a buffer to store uncorrected no action (UCNA) errors for the second memory. The central processor detects a memory data corruption in the second memory, stores a first UCNA error associated with the memory data corruption in the buffer implemented within the first memory, determines whether the buffer is full, and erases an oldest in time UCNA error from the buffer in response to the buffer being full.

Abstract: An information handling system includes a dynamic random access memory, and a processor. The dynamic random access memory includes a lower memory portion and multi-channel dynamic random access memory portion. The dynamic random access memory is allocated to operations of a boot process of the information handling system. The processor communicates with the dynamic random access memory. The processor determines whether a fast memory allocation service is detected in the boot process. In response to the fast memory allocation being detected, the processor allocates the multi-channel dynamic random access memory portion of the dynamic random access memory to operations of the boot process.

Abstract: An on-package multi-channel dynamic random access memory stores data associated with write requests. An off-package memory stores a copy of the data associated with the write requests. A resiliency driver detects a write request, stores data for the write request to the on-package multi-channel dynamic random access memory as a primary image, stores a backup of the data for the write request to the off-package memory as a secondary image, detects a read request, and reads data for the read request from the on-package multi-channel dynamic random access memory as the primary image.

Abstract: An on-package multi-channel dynamic random access memory stores data associated with write requests. An off-package memory stores a copy of the data associated with the write requests. A resiliency driver detects a write request, stores data for the write request to the on-package multi-channel dynamic random access memory as a primary image, stores a backup of the data for the write request to the off-package memory as a secondary image, detects a read request, and reads data for the read request from the on-package multi-channel dynamic random access memory as the primary image.

Abstract: An information handling system includes a central processing unit, which in turn includes a system memory and a first processor core. The system memory stores Common Platform Error Record (CPER) entries in a queue. The first processor core stores the hardware error in a bank of a machine check bank register of the first processor core, and generates a system management interrupt (SMI) in response to storing the hardware error in the bank. The central processing unit receives the generated SMI, clears CPER entries within the queue of the system memory that are outside a specific timespan before a corrected machine check error indication associated with the generated SMI is received, adds a CPER entry associated with the corrected machine check error indication to the queue of the system memory, and disables SMI generation from the machine check bank number in response to the number of CPER entries exceeding the threshold count.

Abstract: An information handling system includes a central processing unit, which in turn includes a system memory and a first processor core. The system memory stores Common Platform Error Record (CPER) entries in a queue. The first processor core stores the hardware error in a bank of a machine check bank register of the first processor core, and generates a system management interrupt (SMI) in response to storing the hardware error in the bank. The central processing unit receives the generated SMI, clears CPER entries within the queue of the system memory that are outside a specific timespan before a corrected machine check error indication associated with the generated SMI is received, adds a CPER entry associated with the corrected machine check error indication to the queue of the system memory, and disables SMI generation from the machine check bank number in response to the number of CPER entries exceeding the threshold count.

Abstract: An information handling system includes a first memory, a second memory, and a central processor. The first memory includes a buffer to store uncorrected no action (UCNA) errors for the second memory. The central processor detects a memory data corruption in the second memory, stores a first UCNA error associated with the memory data corruption in the buffer implemented within the first memory, determines whether the buffer is full, and erases an oldest in time UCNA error from the buffer in response to the buffer being full.

Abstract: An information handling system includes a dynamic random access memory, and a processor. The dynamic random access memory includes a lower memory portion and multi-channel dynamic random access memory portion. The dynamic random access memory is allocated to operations of a boot process of the information handling system. The processor communicates with the dynamic random access memory. The processor determines whether a fast memory allocation service is detected in the boot process. In response to the fast memory allocation being detected, the processor allocates the multi-channel dynamic random access memory portion of the dynamic random access memory to operations of the boot process.