Abstract: Utility vehicles include ground engaging members, a frame supported by the ground engaging members, a motor supported by the frame operably coupled to the ground engaging members, and a battery configured to provide electrical power to the motor. The battery may be removable and configured to be easily charged by outside power sources such as generators and external batteries. A charger may be configured to receive instructions to charge the battery using a specific charger operating characteristic. The vehicle may also include a variety of accessory ports configured to electrically couple to accessories that use AC or DC power.

Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector provides electrons for substrate hot electron injection of electrons onto the floating gate for programming. The cell depletion/inversion region may be extended by forming a capacitor as an extension of the control gate over the substrate between the source and channel of said sense transistor.

Abstract: An integrated circuit die include a first portion including logic circuits. A second portion of the die includes an EEPROM memory, and a third portion includes a FLASH memory.

Abstract: An integrated circuit die include a first portion including logic circuits. A second portion of the die includes an EEPROM memory, and a third portion includes a FLASH memory.

Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector provides electrons for substrate hot electron injection of electrons onto the floating gate for programming. The cell depletion/inversion region may be extended by forming a capacitor as an extension of the control gate over the substrate between the source and channel of said sense transistor.

Abstract: A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).

Abstract: A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).

Abstract: An antifuse structure (20) and method of fabrication are provided. A first conductive layer (A) is etched according to a first mask (62a) having a first pattern and according to a second mask (64a) having a second pattern. A first insulative layer (30) is disposed over the first conductive layer (A) and etched according to a third mask (40a) having a third pattern to expose at least one section of the first conductive layer (A). A second insulative layer (26) is disposed adjacent at least one exposed section of the first conductive layer (A). A second conductive layer (1) is disposed over the second insulative layer (26) so that the antifuse structure (20) includes at least one antifuse region (A1) where a section of the second insulative layer (26) is adjacent the first (A) and second (1) conductive layers. The antifuse region (A1) has a sublithographic vertical dimension (t) according to a thickness of the first conductive layer (A).

Abstract: A method and resulting structure to provide an antifuse wherein the resistance of the programmed fuse and the line resistance and capacitance are materially reduced relative to the prior art and the procedures involved and the resulting structure of the fuse permit the use of materials not available in prior art antifuses. This is accomplished by providing the fuse on vertical sidewalls of the fuse electrode or beneath a sidewall oxide on the fuse electrode. Since the thickness of the electrode can be controlled to an extent not currently achievable by lithographic means, a much smaller area antifuse is provided using sidewall antifuse as opposed to a planar antifuse.

Abstract: A described embodiment of the present invention includes an anti-fuse comprising: a first conductive layer having a horizontal major surface and having a substantially vertical sidewall; a thick insulating layer formed on the horizontal major surface of the first conductive layer; a dielectric layer formed on the vertical sidewall; and a second conductive layer formed on the dielectric layer. In an additional embodiment, the first and/or second conductive layers comprise polycrystalline silicon and a conductive material selected from the group of titanium, tungsten, molybdenum, platinum, titanium silicide, tungsten silicide, molybdenum silicide, platinum silicide, titanium nitride and combinations thereof.

Abstract: A source side injection non-volatile memory cell is provided that comprises a floating gate and control gate stack (12) disposed outwardly from a channel region (26) formed on an (n-)-substrate (10). Drain region (32) and source region (30) are formed on opposite sides of stack structure (12). Source side injection of hot electrons occurs between source region (30) and floating gate (18) when relatively low voltages are placed on gate conductor (22).

Abstract: A method and resulting structure to provide an antifuse wherein the resistance of the programmed fuse and the line resistance and capacitance are materially reduced relative to the prior art and the procedures involved and the resulting structure of the fuse permit the use of materials not available in prior art antifuses. This is accomplished by providing the fuse on vertical sidewalls of the fuse electrode or beneath a sidewall oxide on the fuse electrode. Since the thickness of the electrode can be controlled to an extent not currently achievable by lithographic means, a much smaller area antifuse is provided using sidewall antifuse as opposed to a planar antifuse.

Abstract: A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).

Abstract: Method and apparatus for formation of an alloy thin film, or a mixed metal oxide thin film, on a substrate at relatively low temperatures. Precursor vapor(s) containing the desired thin film constituents is positioned adjacent to the substrate and irradiated by light having wavelengths in a selected wavelength range, to dissociate the gas(es) and provide atoms or molecules containing only the desired constituents. These gases then deposit at relatively low temperatures as a thin film on the substrate. The precursor vapor(s) is formed by vaporization of one or more precursor materials, where the vaporization temperature(s) is selected to control the ratio of concentration of metals present in the precursor vapor(s) and/or the total precursor vapor pressure.

Abstract: A field programmable gate array having anti-fuse crosspoints. The input and output circuits of the gate array are especially designed so that the low voltage logic modules are not affected by high programming voltages. Each logic module is designed to be part of the programming circuit, rather than being isolated from it.

Abstract: Exhaust gases are treated to remove NO or NO.sub.x and SO.sub.2 by contacting the gases with an aqueous emulsion or suspension of yellow phosphorus preferably in a wet scrubber. The pressure is not critical, and ambient pressures are used. Hot water temperatures are best, but economics suggest about 50.degree. C. are attractive. The amount of yellow phosphorus used will vary with the composition of the exhaust gas, less than 3% for small concentrations of NO, and 10% or higher for concentrations above say 1000 ppm. Similarly, the pH will vary with the composition being treated, and it is adjusted with a suitable alkali. For mixtures of NO.sub.x and SO.sub.2, alkalis that are used for flue gas desulfurization are preferred. With this process, 100% of the by-products created are usable, and close to 100% of the NO or NO and SO.sub.2 can be removed in an economic fashion.

Abstract: Circuitry 12 is formed at the face of a layer semiconductor 34. The circuitry includes a plurality of contact points 22 and 24. At least one anti-fuse 14 is formed in a layer vertically displaced from circuitry 12. Anti-fuse 14 is operable to selectively connect together certain ones of said contact points 22 and 24.

Abstract: Exhaust gases are treated to remove NO or NO.sub.x and SO.sub.2 by contacting the gases with an aqueous emulsion or suspension of yellow phosphorous preferably in a wet scrubber. The addition of yellow phosphorous in the system induces the production of O.sub.3 which subsequently oxidizes NO to NO.sub.2. The resulting NO.sub.2 dissolves readily and can be reduced to form ammonium ions by dissolved SO.sub.2 under appropriate conditions. In a 20 acfm system, yellow phosphorous is oxidized to yield P.sub.2 O.sub.5 which picks up water to form H.sub.3 PO.sub.4 mists and can be collected as a valuable product. The pressure is not critical, and ambient pressures are used. Hot water temperatures are best, but economics suggest about 50.degree. C. The amount of yellow phosphorus used will vary with the composition of the exhaust gas, less than 3% for small concentrations of NO, and 10% or higher for concentrations above say 1000 ppm.

Abstract: The present invention in one aspect relates to a process for the simultaneous removal of NO.sub.x and SO.sub.2 from a fluid stream comprising mixtures thereof and in another aspect relates to the separation, use and/or regeneration of various chemicals contaminated or spent in the process and which includes the steps of:(A) contacting the fluid stream at a temperature of between about 105.degree. and 180.degree. C.

Abstract: A method of removing nitrogen monoxide from a nitrogen monoxide-containing gas, which method comprises:(a) contacting a nitrogen oxide-containing gas with an aqueous solution of water soluble organic compound-iron ion chelate of the formula: ##STR1## wherein the water-soluble organic compound is selected from compounds of the formula: ##STR2## wherein: R is selected from hydrogen or an organic moiety having at least one polar functional group;Z is selected from oxygen, sulfur, or --N--A wherein N is nitrogen and A is hydrogen or lower alkyl having from one to four carbon atoms; andM is selected from hydrogen, sodium or potassium; andn is 1 or 2, in a contacting zone for a time and at a temperature effective to reduce the nitrogen monoxide. These mixtures are useful to provide an unexpensive method of removing NO from gases, thus reducing atmospheric pollution from flue gases.