Abstract: Detecting a radio frequency (RF) environment around a computer and using a power management scheme for an RF user input device being used by the computer system. If the computer system is in a single user environment, a power management scheme may be used to conserve power on the RF user input device. If the computer system is in a multi-user environment, a power management scheme may be used to minimize interference between neighboring computer systems by minimizing the signal strength of the RF signal from the RF user input device and the RF signal from the computer system.

Abstract: An oscillator circuit. In one embodiment, the oscillator includes a gain circuit, an envelope detector, and an amplitude comparison circuit. The trans-conductance circuit is configured to amplify a periodic signal produced by a crystal. Amplitude peaks of the periodic signal may be detected in the envelope detector, which may determine an average amplitude value based on the detected peaks. The average amplitude value may be compared to a DC voltage value in an amplitude comparison circuit. The DC voltage value may include both a DC average of the periodic signal as well as a predetermined DC offset value. The gain circuit may adjust the level of amplification of the periodic signal based on a feedback signal in order to ensure that the oscillator produces a periodic output signal at a desired level so as to insure oscillation and the minimum use of current to achieve oscillations.

Abstract: Detecting a radio frequency (RF) environment around a computer and using a power management scheme for an RF user input device being used by the computer system. If the computer system is in a single user environment, a power management scheme may be used to conserve power on the RF user input device. If the computer system is in a multi-user environment, a power management scheme may be used to minimize interference between neighboring computer systems by minimizing the signal strength of the RF signal from the RF user input device and the RF signal from the computer system.

Abstract: An oscillator circuit. In one embodiment, the oscillator includes a gain circuit, an envelope detector, and an amplitude comparison circuit. The trans-conductance circuit is configured to amplify a periodic signal produced by a crystal. Amplitude peaks of the periodic signal may be detected in the envelope detector, which may determine an average amplitude value based on the detected peaks. The average amplitude value may be compared to a DC voltage value in an amplitude comparison circuit. The DC voltage value may include both a DC average of the periodic signal as well as a predetermined DC offset value.

Abstract: A correction circuit (10) includes a transistor (30) that generates a feedback signal for equalizing the amplitude and adjusting the phase of the output signals (V.sub.OUT- and V.sub.OUT+) that are provided at the output of the variable gain amplifier (10). The base terminal of the transistor (30) receives a summed value of the output signals (V.sub.OUT- and V.sub.OUT+). The summed value is inverted and fed back to the differential transistors (12 and 14) and combined with the output signals (V.sub.OUT- and V.sub.OUT+). The output signals (V.sub.OUT- and V.sub.OUT+) have a proper amplitude and phase relationship when the summed value is substantially zero.

Abstract: A PLL system (10) includes a PFD (24) that receives a reference clock signal (REF CLK) and a feedback clock signal (FBK CLK). The PFD (24) generates an analog signal (TUNE) based on the phase and frequency relationship of the reference and feedback clock signals. The PFD (24) also generates a clock signal based on two PI phase slips for clocking a counter (70). The analog signal is compared against an upper and lower reference voltage in a threshold detect circuit (34) and the signals UP and DOWN supplied to the counter (70). The counter (70) provides a count value that controls the resonant frequency generated by a tank circuit (73). The tuning range of an oscillator (18) is extended by changing the capacitance of the tank circuit (73).

Abstract: An RF mixer (10) provides signal gain in a transconductor block (12). A first transistor (36) is sized M times larger than a second transistor (18) to generate the desired signal gain. The gain of the RF mixer (10) is the value M times an output impedance Z.sub.OUT divided by an input impedance Z.sub.IN. A first current (I.sub.40) conducted by the first transistor (36) is matched to a sum of the second current (I.sub.24) conducted by the second transistor (18) and a third current (I.sub.28). The first current is supplied to a first differential transistor pair (46, 48) and the summed current is supplied to a second differential transistor pair (56, 58) to provide balance in switching circuit (50).

Abstract: A wireless communication system (10) uses a phase detector (28) having a first pair of flip-flops (50, 56) for detecting the phase difference between an input frequency and a reference frequency. The first pair of flip-flops control current sources (66, 70) in the charge pump of the phase detector to modulate the error signal. A second pair of flip-flops (52, 58) detect when the input frequency is more than 2.pi. ahead of or behind the reference frequency. The second pair of flip-flops increment and decrement a counter (54) which in turn controls additional current sources (78-88) in the charge pump. The additional current sources extend the linear operating range of the error signal when the phase error exceeds .+-.2.pi..

Abstract: An RF buffer (10) supplies a single ended output signal and differential output signals. An average voltage of the differential output signals is compared to a reference voltage (VR) by an amplifier (40). The amplifier (40) provides a feedback signal for controlling the bias current conducted by a first transistor (24) and a mirrored bias current conducted by a second transistor (46). The bias currents conducted by the first and second transistors (24, 46) are used to generate the differential output signals (OUT-, OUT+) and are substantially independent of the signal level at an input terminal (20). The signal current conducted by the first transistor (24) controls an output transistor (66), while the signal current conducted by the second transistor (46) controls another output transistor (56) in the push-pull output stage of the RF buffer (10).

Abstract: A differential amplifier (10) receives a differential input signal (V.sub.IN). The input signal is attenuated by a first attenuator (12) and applied to a tan h amplifier (16). The input signal is also attenuated by a second attenuator (14) and applied to a sin h amplifier (18). The input signals to the tan h amplifier and sin h amplifier are independently attenuated. The transfer functions of the tan h amplifier and the sin h amplifier each have a linear region and a non-linear region. The output of the tan h amplifier and the sin h amplifier are summed (26) so that the non-linear region of the tan h amplifier cancels with the non-linear region of the sin h amplifier. The overall transfer function of the differential amplifier is linear over a wide range of input signal amplitudes by the cancellation of the non-linear regions.

Abstract: A circuit and method for producing a phase shifted quadrature signal (VOUT) from an in-phase signal (VIN). The in-phase signal (VIN) is applied to the control electrode of a voltage follower (121). The voltage follower (121) has a variable output resistance which combines with a capacitor (123) to delay the input signal (VIN) in accordance with the time constant formed by the variable output resistance and the capacitor (123). The variable output resistance is controlled by adjusting the bias current of the voltage follower (121) with a control signal.

Abstract: A circuit and method for reducing a phase error at the output terminal (48) of a multiplier circuit (41) is provided. The phase error arises when first and second input signals having asymmetric signal paths are multiplied in the multiplier circuit (41). A second multiplier circuit (42) multiplies the in-phase and quadrature signals and produces an output signal at an output terminal (49) which contains the phase error but with the opposite polarity as the phase error produced by the first multiplier circuit (41). The signals at the output terminals (48) and (49) are summed in a summing circuit (43) to produce a third output signal in which the phase error is canceled.

Abstract: A base current compensation circuit (10) generates a current that tracks a gain of a transistor (11). The compensation circuit (10) includes a current mirror formed by a mirror transistor (12) and an output transistor (14). The mirror transistor (12) is connected to the transistor (11) whose gain is tracked. A current source (16) and a feedback transistor (13) causes the mirror transistor (12) to draw a base current from the transistor (11) so that a collector current of the transistor (11) matches a reference current. The output transistor (14) amplifies the base current of the transistor (11) to generate the tracking current in the collector electrode of the output transistor (14).

Abstract: A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.