Abstract: A method for storing data includes determining, using a first match line, that a match word satisfies a first content addressable memory (CAM) word stored in a CAM array, wherein the CAM array is configured to store a second CAM word that matches the first CAM word. The method further includes determining that a first parity bit associated with the first CAM word matches a first parity of the first CAM word. The method further includes, in response to determining that the first parity bit associated with the first CAM word matches the first parity determining, using the first match line, a first random access memory (RAM) word stored in a RAM array and outputting the first RAM word.

Abstract: A method for storing data includes determining, using a first match line, that a match word satisfies a first content addressable memory (CAM) word stored in a CAM array, wherein the CAM array is configured to store a second CAM word that matches the first CAM word. The method further includes determining that a first parity bit associated with the first CAM word matches a first parity of the first CAM word. The method further includes, in response to determining that the first parity bit associated with the first CAM word matches the first parity determining, using the first match line, a first random access memory (RAM) word stored in a RAM array and outputting the first RAM word.

Abstract: A configuration for a carbon nanotube (CNT) based memory device can include multiple CNT elements in order to increase memory cell yield by reducing the times when a memory cell gets stuck at a high state or a low state.

Abstract: A desired current through a carbon nano tube (CNT) element of a CNT memory device can be controlled by a wordline voltage, and a voltage on the CNT common node can be held constant. The common node can be constant at a source voltage if a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) is used in the CNT memory device, or the common node can be constant at a supply voltage if an n-channel MOSFET is used in the CNT memory device.

Abstract: A programmable impedance based memory device includes a programmable impedance element, read circuitry configured to determine a resistance of the programmable impedance element during a write operation; and, write circuitry configured to change the resistance of the programmable impedance element as part of performing the write operation, wherein the write circuitry is further configured to terminate the write operation based on the read circuitry detecting that the resistance of the programmable impedance element has passed a threshold value.

Abstract: A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal and its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage that offsets parasitic leakage current in the programmable switch circuit that can result in improper enable signal output. A high resistance direct path to ground on an output node of the power-on reset circuit prevents residual charge from causing an undesired misfire.

Abstract: A configuration for a carbon nanotube (CNT) based memory device can include multiple CNT elements in order to increase memory cell yield by reducing the times when a memory cell gets stuck at a high state or a low state.

Abstract: A desired current through a carbon nano tube (CNT) element of a CNT memory device can be controlled by a wordline voltage, and a voltage on the CNT common node can be held constant.

Abstract: A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.

Abstract: A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal arid its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage, offsetting parasitic leakage current in the programmable switch circuit that can result in improper enable signal output.

Abstract: A hardening system includes a data storage device having a data input, a clock input, a data node Q, and a data complement node QN. The data storage device provides drive to the data node Q and the data complement node QN. A hardening circuit includes first, second, third, fourth, and fifth transistor circuits. The first and second transistor circuits form a first node therebetween, and the first transistor circuit prevents the data node Q from changing states in the presence of radiation. The third and fourth transistor circuits form a second node therebetween, and the third transistor circuit prevents the data complement node QN from changing states in the presence of radiation. The first node is coupled to the third transistor circuit, and the second node is coupled to the first transistor circuit. The fifth transistor circuit prevents the first and second nodes from floating.

Abstract: A hardening system includes a data storage device having a data input, a clock input, a data node Q, and a data complement node QN. The data storage device provides drive to the data node Q and the data complement node QN. A hardening circuit includes first, second, third, fourth, and fifth transistor circuits. The first and second transistor circuits form a first node therebetween, and the first transistor circuit prevents the data node Q from changing states in the presence of radiation. The third and fourth transistor circuits form a second node therebetween, and the third transistor circuit prevents the data complement node QN from changing states in the presence of radiation. The first node is coupled to the third transistor circuit, and the second node is coupled to the first transistor circuit. The fifth transistor circuit prevents the first and second nodes from floating.