Abstract: A system and method for remote regulation of a switching power converter operating relative to a second ground is disclosed where a control signal is produced by comparing the line voltage relative to a first ground with a reference voltage relative to the first ground to produce a first error signal relative to the first ground, translating the first error signal to a second error signal relative to a second ground, and applying the second error signal to the switching power converter to thereby regulate the switching power converter as a function of the line voltage.

Abstract: A system and method for remote regulation of a switching power converter operating relative to a second ground is disclosed where a control signal is produced by comparing the line voltage relative to a first ground with a reference voltage relative to the first ground to produce a first error signal relative to the first ground, translating the first error signal to a second error signal relative to a second ground, and applying the second error signal to the switching power converter to thereby regulate the switching power converter as a function of the line voltage.

Abstract: A space vehicle includes a temperature sensitive oscillator carried by a housing. The temperature sensitive oscillator includes a radiation hardened inverting gain circuit, such as a comparator, able to withstand radiation in an ambient space environment, and a thermistor connected to the radiation hardened inverting gain circuit so that an output frequency of the temperature sensitive oscillator varies based upon a temperature of the thermistor. Also, a frequency counter is preferably connected to the temperature sensitive oscillator for generating a digital output signal representative of a sensed temperature. The sensed temperature may be used by one or more electronic circuits connected to the frequency counter.

Abstract: A "just in time" pipelined signal processing architecture for a phased array antenna simultaneously updates the weights of all phase control elements of the antenna with reduced wiring complexity and fast beam steering updates. Signal propagation paths between a pipelined communication link--through subarray control processors distributed along the pipeline link--and phase control elements of the antenna array are provided with respectively different serial pipelined transport delays. These delays are such that all phase control signals produced by the subarray control processors are applied simultaneously to their associated subsets of antenna phase control elements. The use of serial (FIFO) delays to equalize pipeline and weight processing latency allows each subarray controller to process and forward serial beam vector data at the same data rate at which it is received from an upstream host processor.

Abstract: A variable die size gate array architecture is realizable by forming in a semiconductor substrate an array of circuit devices separated from one another by a network of routing channels. Through the selective interconnection of the routing channels and the circuit devices a prescribed signal processing function may be implemented. The array of circuit devices includes gate supercells each of which is configurable to perform a respective signal processing operation, and input/output supercells each of which is configurable to effectively perform input/output interfacing between the gate supercells and signal terminals external to the array. The gate supercells and the input/output supercells are intermingled with one another in the array in accordance with a prescribed two-dimensional distribution pattern.

Abstract: A variable die size gate array architecture is realizable by forming in a semiconductor substrate an array of circuit devices separated from one another by a network of routing channels. Through the selective interconnection of the routing channels and the circuit devices a prescribed signal processing function may be implemented. The array of circuit devices includes gate supercells each of which is configurable to perform a respective signal processing operation, and input/output supercells each of which is configurable to effectively perform input/output interfacing between the gate supercells and signal terminals external to the array. The gate supercells and the input/output supercells are intermingled with one another in the array in accordance with a prescribed two-dimensional distribution pattern.

Abstract: A high-resolution digital pulse to digital pulse divider circuit directly synthesizes precise frequencies having low phase noise content and phase continuity when frequency changes occur.

Abstract: A mixer-driver circuit in a code correlator of a spread-spectrum communications system simultaneously multiplies an input RF signal with two phase-offset digitally encoded bit streams. A double-balanced mixer is driven with the difference of the digital signals; the mixer is either inverting, noninverting, or off. Matched ECL bistables which reclock the phase-offset bit streams, and a load current steering circuit coupled to the bistables together provide a balanced, differential drive current to the mixer which switches state faster than the bistables alone. In another embodiment, a single bistable receiving an encoded bit stream differentially drives the mixer in a biphase circuit.

Abstract: An electronic time-of-day clock having a low-power time source and compensation circuits selectively operable responsive to pulses output from the low-power time source when system primary power is off or disabled, and responsive to a relatively highly accurate time-pulse generator when primary power is enabled. The time-of-day clock compensates continuously in real-time for errors in the output of the low-power time source caused by variations in the ambient temperature of the device; when primary power is enabled, the output of the low-power time source is further compensated by comparing the output thereof with the output of the high-accuracy frequency standard and storing accumulated error.

Abstract: A mixer-driver circuit in a code correlator of a spread-spectrum communications system simultaneously multiplies an input RF signal with two phase-offset digitally encoded bit streams. A double-balanced mixer is driven with the difference of the digital signals; the mixer is either inverting, noninverting, or off. Matched ECL bistables which reclock the phase-offset bit streams, and a load current steering circuit coupled to the bistables together provide a balanced, differential drive current to the mixer which switches state faster than the bistables alone. In another embodiment, a single bistable receiving an encoded bit stream differentially drives the mixer in a biphase circuit.