Abstract: In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

Abstract: A spectrometer is designed capable of effectively covering the full desired spectral range using an array of multiple diffraction gratings arranged in gradually differentiated angles to diffract certain sub-range of photon wavelengths to the target detectors without relying on mechanically changing gratings or use of any moving parts. The optically subdivided spectral analysis results are then electronically integrated to accurately yield the desired full range spectral measurement at a speed compatible to the limit of optical and digital analyzers' speed of the measuring system without manual adjustment and/or mechanical movement delays.

Abstract: A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

Abstract: A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which is contacted and driven separately from the conventional gate of the transistor. The gate spacer, conductive layer of a composite spacer or a portion or portions thereof serve as a control or controls for the transistors taking the form of a second gate or second and third gates for the transistors. The transistors may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistors are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors.

Abstract: Embodiments of the invention provide thermally actuatable switches and selectively configurable circuit boards which may employ such switches. A circuit board of one embodiment includes a substrate having board leads and a plurality of electrical connectors arranged adjacent a component site. Selectively configurable circuitry may be carried by the substrate and adapted to selectively couple selected ones of the electrical connectors to selected ones of the board leads. One or more trace may be associated with each of the electrical connectors and one or more of these traces may include a thermally actuatable switch that can be selectively closed. The thermally actuatable switch may comprise a gap between two conductive lengths of the conductive trace, an exposed switch surface, and a thermally responsive member that may wet the exposed switch surface when selectively heated above an activation temperature.

Abstract: Embodiments of the invention provide thermally actuatable switches and selectively configurable circuit boards which may employ such switches. A circuit board of one embodiment includes a substrate having board leads and a plurality of electrical connectors arranged adjacent a component site. Selectively configurable circuitry may be carried by the substrate and adapted to selectively couple selected ones of the electrical connectors to selected ones of the board leads. One or more trace may be associated with each of the electrical connectors and one or more of these traces may include a thermally actuatable switch that can be selectively closed. The thermally actuatable switch may comprise a gap between two conductive lengths of the conductive trace, an exposed switch surface, and a thermally responsive member that may wet the exposed switch surface when selectively heated above an activation temperature.

Abstract: In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

Abstract: A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

Abstract: Embodiments of the invention provide thermally actuatable switches and selectively configurable circuit boards which may employ such switches. A circuit board of one embodiment includes a substrate having board leads and a plurality of electrical connectors arranged adjacent a component site. Selectively configurable circuitry may be carried by the substrate and adapted to selectively couple selected ones of the electrical connectors to selected ones of the board leads. One or more trace may be associated with each of the electrical connectors and one or more of these traces may include a thermally actuatable switch that can be selectively closed. The thermally actuatable switch may comprise a gap between two conductive lengths of the conductive trace, an exposed switch surface, and a thermally responsive member that may wet the exposed switch surface when selectively heated above an activation temperature.

Abstract: Embodiments of the invention provide thermally actuatable switches and selectively configurable circuit boards which may employ such switches. A circuit board of one embodiment includes a substrate having board leads and a plurality of electrical connectors arranged adjacent a component site. Selectively configurable circuitry may be carried by the substrate and adapted to selectively couple selected ones of the electrical connectors to selected ones of the board leads. One or more trace may be associated with each of the electrical connectors and one or more of these traces may include a thermally actuatable switch that can be selectively closed. The thermally actuatable switch may comprise a gap between two conductive lengths of the conductive trace, an exposed switch surface, and a thermally responsive member that may wet the exposed switch surface when selectively heated above an activation temperature.

Abstract: A method and apparatus invention that relates to the reduction of leakage current through a tunnel oxide layer of a memory cell to improve data retention. One method of operating a non-volatile memory cell comprises placing electrons on a floating gate of the memory cell and then placing positive charge on a control gate of the memory cell to improve data retention. The positive charge causes the electrons on the floating gate to migrate away from a tunnel oxide layer of the memory cell. In one embodiment, a Flash memory device comprises a memory array of multiple memory cells. Each memory cell comprises a control gate, a floating gate, an inter-gate dielectric layer positioned between the control gate and the floating gate, a substrate, and a tunnel oxide layer positioned between the floating gate and the substrate.

Abstract: A method and apparatus invention that relates to the reduction of leakage current through a tunnel oxide layer of a memory cell to improve data retention. One method of operating a non-volatile memory cell comprises placing electrons on a floating gate of the memory cell and then placing positive charge on a control gate of the memory cell to improve data retention. The positive charge causes the electrons on the floating gate to migrate away from a tunnel oxide layer of the memory cell. In one embodiment, a Flash memory device comprises a memory array of multiple memory cells. Each memory cell comprises a control gate, a floating gate, an inter-gate dielectric layer positioned between the control gate and the floating gate, a substrate, and a tunnel oxide layer positioned between the floating gate and the substrate.

Abstract: A motorized scooter includes a platform (20), a steering column (10) pivotally secured to a front of the platform (20), a front wheel (12) mounted to the steering column (10), a rear wheel (14) mounted to the rear of the platform (20), a power train (30) extending between the platform (20) and the rear wheel (14) and a motor (32). The power train (30) has a driving sprocket (34), a driven sprocket (38), a chain (36) reeved around the driving and driven sprockets (34, 38), and a bracket (39) supporting the axle (322) and the driving sprocket (34). A freewheel mechanism (342) is fitted in the driving sprocket (34) whereby in a driving mode the turning axle (322) indirectly turns the rear wheel (14), and in a freewheel mode the turning rear wheel (14) does not result in the turning of the motor (32).

Abstract: An SRAM memory cell is provided in which a pair of cross-coupled n-type MOS pull-down transistors are coupled to respective parasitically formed bipolar pull-up transistors. The memory cell is formed within a semiconductor layer which extends over a buried layer. The bipolar transistors are formed parasitically from the buried layer and the semiconductor layer used to form the pull-down transistors. The bases of the bipolar transistors may also be dynamically controlled. An SRAM memory array having a plurality of such memory cells and a computer system incorporating the SRAM memory array are also provided.

Abstract: A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which is contacted and driven separately from the conventional gate of the transistor. The gate spacer, conductive layer of a composite spacer or a portion or portions thereof serve as a control or controls for the transistors taking the form of a second gate or second and third gates for the transistors. The transistors may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistors are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors.

Abstract: Conductive interconnections are formed by depositing an adhesive material, made up of ferromagnetic particles dispersed within a matrix material, on a semiconductor substrate, such as an electronic component, and applying a magnetic field between an exposed surface of the adhesive material and an attached surface of the adhesive material (abutting the semiconductor substrate), such that a plurality of the ferromagnetic particles move and align within the matrix material under the influence of the magnetic field. One method of the present invention comprises depositing the adhesive material on a contact site of a first electronic component. A second electronic component having a contact site is aligned over the adhesive material and a magnetic field is applied between the first electronic component and the second electronic component.

Abstract: A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which contacted and driven separately from the conventional gate of the transistor. The gate spacer, conductive layer of a composite spacer or a portion or portions thereof serve as a control or controls for the transistors taking the form of a second gate or second and third gates for the transistors. The transistors may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistors are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors.

Abstract: A semiconductor processing method of forming a field effect transistor includes, a) providing a first layer of material over a substrate; b) providing a first opening through the first layer, the first opening having a width and a base; c) providing a second layer of material over the first layer and to within the first opening to a thickness which is less than one half the first opening width to less than completely fill the first opening and define a narrower second opening; d) anisotropically etching the second layer of material from outwardly of the first layer and from the first opening base to effectively provide inner sidewall spacers within the first opening; e) providing a gate dielectric layer within the second opening; f) providing a layer of electrically conductive gate material over the first layer and to within the second opening over the gate dielectric layer to fill the second opening with conductive gate material; g) without masking, planarize etching the conductive gate material layer substa

Abstract: A memory cell architecture utilizing a dual access gate and dual wordlines is disclosed. The cell is comprised of a first transistor connected between a digitline and a cellplate. The transistor is responsive to a read wordline to enable the cell to be read. An active device, such as a second transistor, is provided for modifying at least one conductive characteristic of the first transistor according to the state of a signal on the digitline. The conductive characteristic that is modified may be, for example, the threshold voltage or the transistor's channel resistance. Modification of the first transistor's characteristics is representative of writing information to the memory cell. A circuit structure for implementing the circuit architecture is also disclosed together with a method of operating a memory cell.

Abstract: An SRAM memory cell is provided in which a pair of cross-coupled n-type MOS pull-down transistors are coupled to respective parasitically formed bipolar pull-up transistors. The memory cell is formed within a semiconductor layer which extends over a buried layer. The bipolar transistors are formed parasitically from the buried layer and the semiconductor layer used to form the pull-down transistors. The bases of the bipolar transistors may also be dynamically controlled. An SRAM memory array having a plurality of such memory cells and a computer system incorporating the SRAM memory array are also provided.