Patents by Inventor David Karchmer
David Karchmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9122826Abstract: A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.Type: GrantFiled: October 11, 2013Date of Patent: September 1, 2015Assignee: Altera CorporationInventors: Terry Borer, Andrew Leaver, David Karchmer, Gabriel Quan, Stephen D. Brown
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Patent number: 8589838Abstract: A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.Type: GrantFiled: July 10, 2012Date of Patent: November 19, 2013Assignee: Altera CorporationInventors: Terry Borer, Andrew Leaver, David Karchmer, Gabriel Quan, Stephen D. Brown
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Patent number: 8572530Abstract: A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed.Type: GrantFiled: December 6, 2010Date of Patent: October 29, 2013Assignee: Altera CorporationInventors: Ryan Fung, Vaughn Betz, David Karchmer
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Patent number: 8516504Abstract: A method or apparatus that allows new devices to be easily integrated with computer aided design (CAD) tools via an easily extensible application programming interface (API). In an embodiment, new devices are added by reading a new device type and assigning a sequential index value. Index values are assigned to the new devices by appending a new device type to the end of an enumeration construct. When the data structure is compiled, the new device type is converted to a sequential index value. Data values for the new device are added to a data structure and can be accessed via the index value. Because the added device type is appended to the end of the enumeration construct, the index values assigned to the original data types remain unchanged. Consequently, recompilation is only required for applications that need to access the new devices and is unnecessary for the applications that do not use the new devices.Type: GrantFiled: January 28, 2003Date of Patent: August 20, 2013Assignee: Altera CorporationInventors: Jim Park, David Karchmer
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Patent number: 8250505Abstract: A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.Type: GrantFiled: December 4, 2009Date of Patent: August 21, 2012Assignee: Altera CorporationInventors: Terry Borer, Andrew Leaver, David Karchmer, Gabriel Quan, Stephen D. Brown
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Patent number: 8161469Abstract: Compiled configuration files for different programmable logic devices that are intended to be functionally equivalent may be compared using multiple different comparisons to assure functional equivalence. The different comparisons include a fitter or resource report comparison, an engineering bit settings report that compares vectors of bits that represent the settings of hard logic blocks, and comparisons based on location, connectivity and functionality. These comparisons are particularly well-suited for determining equivalence between different models of programmable logic devices, or even different types of devices such as field-programmable gate arrays as compared to mask-programmable logic devices.Type: GrantFiled: December 13, 2005Date of Patent: April 17, 2012Assignee: Altera CorporationInventors: Mihail Iotov, Erhard Joachim Pistorius, Jim Park, David Karchmer
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Patent number: 8112728Abstract: A performance estimation module estimates the performance values of user designs in early phases of compilation and accounts for the performance variability introduced by subsequent compilation phases. The user design is parameterized. The performance estimation model outputs a probability distribution function of estimated performance values of the user design, based upon this parameterization. The performance estimation model is created by parameterizing sample designs. The sample designs are compiled and analyzed to determine their performance values. To account for random variability in compilation phases, the module compiles and analyzes sample designs multiple times. The performance estimation model is created from the relationship between sample designs' performance values and their parameterizations. A regression analysis may be used to determine this relationship. The performance estimation model can be updated with the analysis of compiled user designs.Type: GrantFiled: August 11, 2009Date of Patent: February 7, 2012Assignee: Altera CorporationInventors: Michael D. Hutton, David Karchmer
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Patent number: 8001537Abstract: During compilation of a user logic design in a first type of programmable logic device (e.g., an FPGA), a log is kept of at least certain steps where choices are made. When that logic design is migrated to another type of programmable logic device (e.g., a mask-programmable logic device) the logged steps are taken into account to make sure that the same choices are made, so that the target device is functionally equivalent to the original device.Type: GrantFiled: December 5, 2005Date of Patent: August 16, 2011Assignee: Altera CorporationInventors: Mihail Iotov, David Neto, Pouyan Djahani, David Karchmer, Kumara Tharmalingam
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Patent number: 7877721Abstract: Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.Type: GrantFiled: August 16, 2007Date of Patent: January 25, 2011Assignee: Altera CorporationInventors: James G. Schleicher, II, David Karchmer
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Patent number: 7853911Abstract: A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed.Type: GrantFiled: November 4, 2005Date of Patent: December 14, 2010Assignee: Altera CorporationInventors: Ryan Fung, Vaughn Betz, David Karchmer
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Patent number: 7784008Abstract: A visualization displays user designs and performance information at different levels of detail. Related register bits are combined into a metaregister and displayed as a graph node. The set of paths and associated combinatorial logic between two or more metaregisters are collapsed into a metapath and displayed as a graph connection. The set of paths associated with a metapath can be selectively revealed in response to user input. Metapaths can be annotated with performance information of its associated paths, such as timing, area, and power consumption information. The annotated performance information can represent performance information of one or more paths or aggregate attributes of the set of paths. Paths associated with control signals and finite state machines can be identified and displayed as separate graph connections.Type: GrantFiled: January 11, 2006Date of Patent: August 24, 2010Assignee: Altera CorporationInventors: Michael D. Hutton, David Karchmer, Zhiru Zhang
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Patent number: 7725856Abstract: A method for designing a system on a target device is disclosed. Domains and sub-domains in the system are identified. Chunks are identified from the domains and sub-domain. Slacks for the chunks are computed in parallel. Other embodiments are described and claimed.Type: GrantFiled: November 22, 2006Date of Patent: May 25, 2010Assignee: Altera CorporationInventors: Jason Govig, David Karchmer
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Patent number: 7669157Abstract: A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.Type: GrantFiled: September 5, 2006Date of Patent: February 23, 2010Assignee: Altera CorporationInventors: Terry Borer, Andrew Leaver, David Karchmer, Gabriel Quan, Stephen D. Brown
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Patent number: 7587688Abstract: Users or applications provide optimization information that specifies performance-critical portions of the design. Users can identify performance-critical portions of their designs from a priori evaluation of their design or by analyzing the results of previous compilations of their design or similar designs. An application may extract and analyze performance information from previous compilations of the design or similar designs to automatically specify the performance-critical portions of the design. The compilation software uses this specification to focus the appropriate types and amount of optimization on different portions of the design. The compilation software may use additional optimization techniques and/or may allocate additional computing resources to optimize the performance of performance-critical portions of the design. Other portions of the design that are not performance-critical may be optimized using balanced optimization techniques.Type: GrantFiled: August 24, 2006Date of Patent: September 8, 2009Assignee: Altera CorporationInventors: Babette Van Antwerpen, Jinyong Yuan, David Karchmer
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Patent number: 7584443Abstract: The present invention is directed to clock domain conflict analysis of a timing graph that features, dissociating clock domains of one or more of a path having conflicting clock domains while preserving the original clock domain relationship of the edges in the path. To that end, the method includes generating a timing graph having a source instance, a destination instance and a plurality of edges defining a plurality of signal paths between the source instance and the destination instance. A plurality of clock domains is corresponded to the timing graph, with a subset of the plurality of edges being associated with more than one clock domain. From the subset, conflicting clock domains associated with a common edge are identified. In response to identification of the conflict, one of the clock domains is dissociated from one of the edges of the subset.Type: GrantFiled: March 7, 2007Date of Patent: September 1, 2009Assignee: Altera CorporationInventors: Jason Govig, David Karchmer, William Buckner Davis
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Patent number: 7577929Abstract: A performance estimation module estimates the performance values of user designs in early phases of compilation and accounts for the performance variability introduced by subsequent compilation phases. The user design is parameterized. The performance estimation model outputs a probability distribution function of estimated performance values of the user design, based upon this parameterization. The performance estimation model is created by parameterizing sample designs. The sample designs are compiled and analyzed to determine their performance values. To account for random variability in compilation phases, the module compiles and analyzes sample designs multiple times. The performance estimation model is created from the relationship between sample designs' performance values and their parameterizations. A regression analysis may be used to determine this relationship. The performance estimation model can be updated with the analysis of compiled user designs.Type: GrantFiled: July 21, 2005Date of Patent: August 18, 2009Assignee: Altera CorporationInventors: Michael D. Hutton, David Karchmer
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Patent number: 7464362Abstract: A method for designing a system on a target device includes merging a post-fit netlist for a first partition of the system from a set-up compilation with a post-synthesis netlist for a second partition of the system from an incremental compilation to form a combined netlist. Fitting is performed on the combined netlist.Type: GrantFiled: March 20, 2006Date of Patent: December 9, 2008Assignee: Altera CorporationInventors: Terry Borer, David Karchmer, Jason Govig, Andrew Leaver, Gabriel Quan, Kevin Chan, Vaughn Betz, Stephen D. Brown
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Patent number: 7358766Abstract: A mask-programmable logic device includes some circuitry that is electrically programmable as in conventional programmable logic devices. This allows a user to adjust certain characteristics of programmed devices whose logic functions have been proven and need not change, but which operate in an environment that changes, necessitating different characteristics, without having to redesign the programming metallization layers, and therefore without involving the device manufacturer. The programmable elements may include input/output elements, which may need adjustment because the signal characteristics of the larger system change, or clock circuitry, which may need adjustment because environmental conditions such as changes in the expected operating temperature may affect clock signals in the larger system.Type: GrantFiled: May 1, 2006Date of Patent: April 15, 2008Assignee: Altera CorporationInventors: Jimmy Lawson, David Karchmer, Marwan A Khalaf
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Publication number: 20070294659Abstract: Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.Type: ApplicationFiled: August 16, 2007Publication date: December 20, 2007Inventors: James Schleicher, David Karchmer
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Patent number: 7275232Abstract: Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.Type: GrantFiled: April 1, 2005Date of Patent: September 25, 2007Assignee: Altera CorporationInventors: James G. Schleicher, II, David Karchmer