Abstract: Controlling access to an ERST, including: triggering, in response to an occurrence of an error, a SMI; adjusting, in response to the SMI and by a SMM RAS handler module, a slate of an access gate from a locked state to an unlocked state, the access gate controlling access to an ERST storage region; generating, by an OS MCE handler, an error record based on the error; accessing, by the OS MCE handler, an ACPI ERST to identify instructions for storing the error record at the ERST storage region; triggering, in response to the instructions and by the OS MCE handler, an additional SMI; determining, in response to the additional SMI and by a SMM handler, that the access gate is in the unlocked state; in response to determining that the access gate is in the unlocked state: storing, by the SMM handler, the error record at the ERST.

Abstract: An information handling system may perform a quick boot based on a determination that a boot does not require an update to at least one of a firmware and hardware of an information handling system. The information handling system may reboot and may determine whether a boot of the system requires an update to at least one of a firmware and hardware of the information handling system. If the boot does not require an update to the at least one of a firmware and hardware of the information handling system, the information handling system may boot by bypassing one or more basic input/output system (BIOS) power-on self-test (POST) operations.

Abstract: An information handling system may reset components logged in a memory of the information handling system. For example, an information handling system may determine components logged in an information handling system memory and may perform a bulk reset of the logged components.

Abstract: A baseboard management controller (BMC) of an information handling system may notify an operating system of the information handling system of receipt of a firmware update for a PCI component. The operating system of an information handling system may receive a notification from a BMC of the information handling system, via a basic input/output system (BIOS), of the information handling system that the BMC has received the firmware update. The operating system may halt traffic to the PCI component for which an update has been received, and the update may be applied to the component.

Abstract: A baseboard management controller (BMC) of an information handling system may generate a signal to cause the information handling system to reload a kernel of an operating system of the information handling system. The BMC may generate a signal for reloading a kernel of an operating system of an information handling system, and the information handling system may reload the operating system kernel.

Abstract: A processor memory mapped boot system includes a processing system having a processor memory subsystem, and a memory system having at least one memory device. A Basic Input/Output System (BIOS) engine is coupled to the processing system and the memory system, and is configured to begin boot operations and detect a boot memory mode setting for the processor memory subsystem. The BIOS engine configures a memory space that includes the at least one memory device and the processor memory subsystem. In response to detecting the boot memory mode setting, the BIOS engine will configured the processor memory subsystem to provide a first memory region of the memory space. The BIOS engine will then complete boot operations utilizing the processor memory subsystem providing the first memory region of the memory space.

Abstract: Systems and methods for preventing system crashes due to memory link failure in memory mirroring mode in an information handling system (IHS). The IHS may include a first memory device, a second memory device, and an integrated memory controller (IMC). The IMC may issue write transactions to both the first and second memory devices and issue read transactions to the first memory device when the IMC is in memory mirroring mode. The IMC may transmit a system management interrupt (SMI) with an IMC error to a basic input/output system (BIOS) when a persistent uncorrected IMC error is detected within the first memory device. The BIOS may perform a memory mirror failover process that may cause the IMC to issue the write transactions and the read transactions to the second memory device when the IMC error is a fatal memory link error.

Abstract: A baseboard management controller (BMC) of an information handling system may generate a signal to cause the information handling system to reload a kernel of an operating system of the information handling system. The BMC may generate a signal for reloading a kernel of an operating system of an information handling system, and the information handling system may reload the operating system kernel.

Abstract: An information handling system may perform a quick boot based on a determination that a boot does not require an update to at least one of a firmware and hardware of an information handling system. The information handling system may reboot and may determine whether a boot of the system requires an update to at least one of a firmware and hardware of the information handling system. If the boot does not require an update to the at least one of a firmware and hardware of the information handling system, the information handling system may boot by bypassing one or more basic input/output system (BIOS) power-on self-test (POST) operations.

Abstract: An information handling system may reset components logged in a memory of the information handling system. For example, an information handling system may determine components logged in an information handling system memory and may perform a bulk reset of the logged components.

Abstract: A baseboard management controller (BMC) of an information handling system may notify an operating system of the information handling system of receipt of a firmware update for a PCI component. The operating system of an information handling system may receive a notification from a BMC of the information handling system, via a basic input/output system (BIOS), of the information handling system that the BMC has received the firmware update. The operating system may halt traffic to the PCI component for which an update has been received, and the update may be applied to the component.

Abstract: Systems and methods for preventing system crashes due to memory link failure in memory mirroring mode in an information handling system (IHS). The IHS may include a first memory device, a second memory device, and an integrated memory controller (IMC). The IMC may issue write transactions to both the first and second memory devices and issue read transactions to the first memory device when the IMC is in memory mirroring mode. The IMC may transmit a system management interrupt (SMI) with an IMC error to a basic input/output system (BIOS) when a persistent uncorrected IMC error is detected within the first memory device. The BIOS may perform a memory mirror failover process that may cause the IMC to issue the write transactions and the read transactions to the second memory device when the IMC error is a fatal memory link error.

Abstract: A processor memory mapped boot system includes a processing system having a processor memory subsystem, and a memory system having at least one memory device. A Basic Input/Output System (BIOS) engine is coupled to the processing system and the memory system, and is configured to begin boot operations and detect a boot memory mode setting for the processor memory subsystem. The BIOS engine configures a memory space that includes the at least one memory device and the processor memory subsystem. In response to detecting the boot memory mode setting, the BIOS engine will configured the processor memory subsystem to provide a first memory region of the memory space. The BIOS engine will then complete boot operations utilizing the processor memory subsystem providing the first memory region of the memory space.