Abstract: Apparatus and a method for handling nested faults including the steps of determining whether a fault is a first level fault, responding to a determination of a first level fault by saving a first amount of state sufficient to handle a first level fault, and responding to a determination of a nested fault by saving an additional amount of state before handling the fault.

Abstract: A method of maintaining translation context for instructions translated from instructions designed for a target microprocessor to run on a host microprocessor including storing translation context related to each translated host instruction, indicating a translation context for host instructions presently being executed by the host processor, comparing translation context stored for a next host instruction with the translation context for a host instruction presently being executed, executing the next host instruction if the translation context of the next host instruction and the presently executing host instruction compare, and searching for an instruction with translation context which compares to the translation context of the host instruction presently executing if the translation context of the next host instruction and the presently executing host instruction do not compare.

Abstract: An apparatus and method are disclosed for providing visual and audible indications corresponding to the operational status of an electrosurgical generator so that the visual and audible indications can be readily observed and heard within an area normally associated with a working area of a typical operating room. Facilities are provided to mute the audible indication and to indicate that said audible indication has been muted. The indicators preferably include a visual and audible indication corresponding to the RF current delivered by the electrosurgical generator.

Abstract: A method for determining if writes to a memory page are directed to target instructions which have been translated to host instructions in a computer which translates instructions from a target instruction set to a host instruction set, including the steps of detecting a write to a memory page storing target instructions which have been translated to host instructions, detecting whether a sub-area of the memory page to which the write is addressed stores target instructions which have been translated, and invalidating host instructions translated from addressed target instructions.

Abstract: Certain events occurring throughout a microprocessor chip are monitored by a counter system (1) containing a number of digital electronic counters (3, 5, 7 & 9) consolidated at a single location on the processor chip. Those events are communicated to the counter system via electrical leads extending to those functional units in the processor responsible for signaling an event occurrence. Under program control, each counter can be selectively connected (11, 13, 15 & 17) to a selected one of the various functional event producing units. By means of selection logic (19, 21, 23 & 25) separate events originating from multiple functional units may be logically combined, whereby the event counted is a Boolean logic combination of multiple underlying events.

Abstract: An automatic circuit that controls a surgical instrument having a pair of bipolar electrodes. The circuit comprises means for measuring the current between the pair of electrodes, an impedance detection circuit in electrical communication with the current measuring means, a comparator in electrical communication with the impedance detection circuit and a controller electrically connected to the comparator. The impedance detection circuit calculates the impedance between the electrodes based on the measured current and generates a first signal indicative of the calculated impedance. The comparator processes the first signal and generates an activation signal if the calculated impedance falls within a predetermined range of impedance values and generates a deactivation signal if the calculated impedance exceeds a deactivation threshold.

Abstract: A computer implemented process for detecting errors in computer systems including the steps of executing sequences of instructions of a software program on each of a reference system and a test system, detecting and recording state of the reference system and the test system at comparable points in the execution of the program, and comparing the detected state of the reference system and the test system at selectable comparable points in the sequence of instructions including the end of the sequence of instructions. In a particular embodiment, the execution of portions of the sequence of instructions between selectable comparable points on each of the reference system and the test system is automatically replayed if a difference in compared state of the systems is detected.