Abstract: A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.

Abstract: A memory device for extending addressable array space by incorporating virtual and physical memory arrays is disclosed. When extra storage space beyond a physical memory array is needed by a controller of the memory device, the storage space may be provided by extending the address space using a virtual array. The memory device incorporates the use of an extra row address bit to increase the addressable space, whereby the extra bit is utilized to address virtual rows in the virtual array. Spare or redundant physical memory elements utilized for memory repair may be programmed to a virtual address space for the virtual memory array. When a memory device operation is activated, the extra row address bit is set to high, and the virtual row address matches with a spare or redundant memory element, the virtual row in the virtual array space is activated for performance of the operation.

Abstract: Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.

Abstract: Methods, systems, and devices for frequency regulation for memory management commands are described. A memory device may maintain a respective first counter and second counter for each monitoring area of the memory device, where the counters may be incremented for each activate command received for the corresponding monitoring area. If the first counter satisfies a first threshold, an activate command issued to the monitoring area may be ignored. If the second counter fails to satisfy a second threshold, a memory management command issued to the monitoring area may be ignored and the memory device may maintain a value of the second counter, while decrementing the first counter. Alternatively, if the second counter satisfies the second threshold, the memory device may perform a memory management operation associated with a received memory management command and may decrement the first counter and the second counter.

Abstract: Methods, systems, and devices for techniques for non-volatile data protection are described. As part of a power on operation, a non-volatile memory system may be configured to selectively stored data. For example, the memory system may determine whether a host system is authorized to access data stored in the memory system prior to a power off operation. If the memory system determines that the host system is authorized, the memory device may retain the data. If the memory system determines that the host system is not authorized, the memory system may erase all or a portion of the data. In some cases, the memory system may maintain a retain flag to determine whether the host system is authorized. Additionally or alternatively, the memory system may determine whether a password received from the host system is valid to determine whether the host system is authorized.

Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

Abstract: A light wall for cultivating at least one plant indoors may be provided. The light wall may include a first side, a second side, a top side, a bottom side, a front side, and a back side. The light wall may further include a first lighting structure unit disposed within sides of the light wall, and may include a first set of mechanical devices configured to enable movement of the light wall. The first lighting structure may be configured to provide light to the at least one plant through at least the first side. The first set of mechanical devices may be configured to enable movement at least along an axis substantially perpendicular to the first side.

Abstract: A light wall for cultivating at least one plant indoors may be provided. The light wall may include a first side, a second side, a top side, a bottom side, a front side, and a back side. The light wall may further include a first lighting structure unit disposed within sides of the light wall, and may include a first set of mechanical devices configured to enable movement of the light wall. The first lighting structure may be configured to provide light to the at least one plant through at least the first side. The first set of mechanical devices may be configured to enable movement at least along an axis substantially perpendicular to the first side.

Abstract: The present invention is a method and system for audio processing. Embodiments of the present invention may include multi-level equalization capabilities along with room optimization, crossovers, switching, automation control, and scene setting. Embodiments of the present invention may be implemented in the analog or digital realms, or both, and may include channel delays, future proof feature slots, and gain and phase inversion capabilities. The present invention may also include an audio optimization system including an audio processing system and a room correction unit. The room correction unit can cooperate with the audio processing system to generate filter coefficients. The filter coefficients are used by the audio processing system when outputting signals which are amplified by an amplifier and broadcast by a speaker to a particular room. The filter coefficients ensure that the outputted sound is optimized for the particular room.

Abstract: A parallel resonant circuit for removing noise and harmonic frequencies from the AC power source is connected directly in parallel to a power source with no intervening electrical components. The parallel resonant circuit is comprised of at least one inductor for drawing an inductive current that is substantially equal to but one hundred and eight degrees out of phase with at least one capacitor that draws a capacitive current. The capacitors and the inductors of the parallel resonant circuit are connected in parallel and may be tuned to the fundamental frequency of the power line.

Abstract: A parallel resonant circuit for removing noise and harmonic frequencies from the AC power source is connected directly in parallel to a power source with no intervening electrical components. The parallel resonant circuit is comprised of at least one inductor for drawing an inductive current that is substantially equal to but one hundred and eight degrees out of phase with at least one capacitor that draws a capacitive current. The capacitors and the inductors of the parallel resonant circuit are connected in parallel and may be tuned to the fundamental frequency of the power line.