Patents by Inventor David Kirk McAllister
David Kirk McAllister has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240062453Abstract: Systems and techniques are provided for determining bounding regions for a hierarchical structure for ray tracing. For instance, a process can include obtaining an acceleration data structure, the acceleration data structure including one or more primitives of a scene object. A graph cut can be applied to the acceleration data structure. A set of nodes of the acceleration data structure can be determined based on the graph cut, wherein the determined set of nodes is located adjacent to the graph cut. A world-space bounding box can be generated for the scene object, using the set of nodes determined based on the graph cut.Type: ApplicationFiled: November 1, 2023Publication date: February 22, 2024Inventors: David Kirk MCALLISTER, Francois Mathias Robert DEMOULLIN, Alexei Vladimirovich BOURD
-
Patent number: 11893677Abstract: Systems and techniques are provided for widening a hierarchical structure for ray tracing. For instance, a process can include obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure and determining one or more candidate hierarchical acceleration data structures each including the plurality of primitives. A cost metric can be determined for the one or more candidate hierarchical acceleration data structures and, based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures can be determined. An output hierarchical acceleration data structure can be generated based on the compressibility prediction.Type: GrantFiled: July 29, 2022Date of Patent: February 6, 2024Assignee: QUALCOMM IncorporatedInventors: Adimulam Ramesh Babu, Srihari Babu Alla, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar, David Kirk McAllister
-
Publication number: 20240037840Abstract: Systems and techniques are provided for widening a hierarchical structure for ray tracing. For instance, a process can include obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure and determining one or more candidate hierarchical acceleration data structures each including the plurality of primitives. A cost metric can be determined for the one or more candidate hierarchical acceleration data structures and, based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures can be determined. An output hierarchical acceleration data structure can be generated based on the compressibility prediction.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Inventors: Adimulam RAMESH BABU, Srihari Babu ALLA, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR, David Kirk MCALLISTER
-
Patent number: 11861785Abstract: Systems and techniques are provided for determining bounding regions for a hierarchical structure for ray tracing. For instance, a process can include obtaining an acceleration data structure, the acceleration data structure including one or more primitives of a scene object. A graph cut can be applied to the acceleration data structure. A set of nodes of the acceleration data structure can be determined based on the graph cut, wherein the determined set of nodes is located adjacent to the graph cut. A world-space bounding box can be generated for the scene object, using the set of nodes determined based on the graph cut.Type: GrantFiled: February 4, 2022Date of Patent: January 2, 2024Assignee: QUALCOMM IncorporatedInventors: David Kirk McAllister, Francois Mathias Robert Demoullin, Alexei Vladimirovich Bourd
-
Publication number: 20230410407Abstract: Systems and techniques are provided for accelerated shadow ray traversal for a hierarchical structure for ray tracing. For instance, a process can include obtaining a hierarchical acceleration data structure, the hierarchical acceleration data structure including one or more primitives of a scene object. Two or more nodes included in a same level of the hierarchical acceleration data structure can be sorted into a sort order, the sort order based on a sorting parameter value determined for each respective node of the two or more nodes. The sorting parameter value can be associated with a probability of determining a ray-opaque primitive intersection for each respective node of the two or more nodes. An intersection between a shadow ray and an opaque primitive included in a node of the two or more nodes can be determined based on traversing the hierarchical acceleration data structure using the sort order.Type: ApplicationFiled: June 21, 2022Publication date: December 21, 2023Inventors: Piyush GUPTA, David Kirk MCALLISTER
-
Patent number: 11763523Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU or CPU. The apparatus may configure a BVH structure including a plurality of nodes, the BVH structure being associated with geometry data for a plurality of primitives in a scene. The apparatus may also detect a set of hit child nodes for a current node of the plurality of nodes. Further, the apparatus may sort the set of hit child nodes based on the parametric distance value of each of the set of hit child nodes. The apparatus may also compress the node ID and the parametric distance value for each of an updated set of hit child nodes based on the sorted set of hit child nodes. The apparatus may also store the compressed node ID and the compressed parametric distance value for each of the updated set of hit child nodes.Type: GrantFiled: February 4, 2022Date of Patent: September 19, 2023Assignee: QUALCOMM IncorporatedInventors: David Kirk McAllister, Francois Mathias Robert Demoullin
-
Publication number: 20230252727Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU or CPU. The apparatus may configure a BVH structure including a plurality of nodes, the BVH structure being associated with geometry data for a plurality of primitives in a scene. The apparatus may also detect a set of hit child nodes for a current node of the plurality of nodes. Further, the apparatus may sort the set of hit child nodes based on the parametric distance value of each of the set of hit child nodes. The apparatus may also compress the node ID and the parametric distance value for each of an updated set of hit child nodes based on the sorted set of hit child nodes. The apparatus may also store the compressed node ID and the compressed parametric distance value for each of the updated set of hit child nodes.Type: ApplicationFiled: February 4, 2022Publication date: August 10, 2023Inventors: David Kirk MCALLISTER, Francois Mathias Robert DEMOULLIN
-
Publication number: 20230252685Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU or CPU. The apparatus may allocate each of a plurality of primitives in a scene into one of a plurality of bounding boxes, each of the plurality of bounding boxes corresponding to a plurality of nodes including internal nodes and leaf nodes. The apparatus may also identify whether each of the plurality of nodes is one of the internal nodes or one of the leaf nodes. Further, the apparatus may estimate a compressibility of each of the plurality of nodes if the node is one of the leaf nodes, the compressibility of the node corresponding to whether the node is compressible. The apparatus may also compress data corresponding to each of the plurality of nodes if the node is estimated to be compressible.Type: ApplicationFiled: February 4, 2022Publication date: August 10, 2023Inventors: Adimulam RAMESH BABU, Srihari Babu ALLA, David Kirk MCALLISTER
-
Publication number: 20230252717Abstract: Systems and techniques are provided for enhancing operations of a ray tracing processor. For instance, a process can include obtaining one or more nodes of an acceleration data structure. Each node of the one or more nodes includes the same number of bytes. The node(s) can be stored in a cache associated with a ray tracing processor. Each of the stored node(s) are cache line-aligned with the cache associated with the ray tracing processor. A first stored node of the stored node(s) can be provided to the ray tracing processor and processed by the ray tracing processor during a first clock cycle of the ray tracing processor. A second stored node of the stored node(s) can be provided to the ray tracing processor and processed by the ray tracing processor during a second clock cycle of the ray tracing processor.Type: ApplicationFiled: February 4, 2022Publication date: August 10, 2023Inventors: David Kirk MCALLISTER, Fei WEI, Alexei Vladimirovich BOURD
-
Publication number: 20230252726Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU or CPU. The apparatus may configure a BVH structure including a plurality of nodes, the BVH structure being associated with geometry data for a plurality of primitives in a scene. The apparatus may also detect a set of child nodes for a current node of the plurality of nodes. Further, the apparatus may identify a first child node of the set of child nodes based on a node ID of the first child node. The apparatus may also calculate an offset between the node ID of the first child node and a node ID of each of the remaining child nodes in the set of child nodes. The apparatus may also store a representation of the node ID of each of the set of child nodes based on the calculated offset.Type: ApplicationFiled: February 4, 2022Publication date: August 10, 2023Inventors: David Kirk MCALLISTER, Francois Mathias Robert DEMOULLIN
-
Publication number: 20230252716Abstract: Systems and techniques are provided for determining bounding regions for a hierarchical structure for ray tracing. For instance, a process can include obtaining an acceleration data structure, the acceleration data structure including one or more primitives of a scene object. A graph cut can be applied to the acceleration data structure. A set of nodes of the acceleration data structure can be determined based on the graph cut, wherein the determined set of nodes is located adjacent to the graph cut. A world-space bounding box can be generated for the scene object, using the set of nodes determined based on the graph cut.Type: ApplicationFiled: February 4, 2022Publication date: August 10, 2023Inventors: David Kirk MCALLISTER, Francois Mathias Robert DEMOULLIN, Alexei Vladimirovich BOURD
-
Publication number: 20230252725Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may configure a BVH structure including a plurality of nodes each including one or more primitives, and each of the primitives being associated with a primitive ID, a geometry ID, and a set of floating-point coordinates. The apparatus may also compress the primitive ID or the geometry ID for each of the primitives. Further, the apparatus may convert a binary representation of each of the floating-point coordinates into an integer value of each of the floating-point coordinates. The apparatus may also calculate a difference between the integer value of each of the set of floating-point coordinates for each of the plurality of primitives. The apparatus may also store the compressed primitive ID or the compressed geometry ID and the calculated difference.Type: ApplicationFiled: February 4, 2022Publication date: August 10, 2023Inventor: David Kirk MCALLISTER
-
Patent number: 11593990Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may configure a BVH structure including a plurality of levels and a plurality of nodes, the BVH structure being associated with geometry data for a plurality of primitives in a scene. The apparatus may also identify an amount of storage in a GMEM that is available for storing at least some of the plurality of nodes in the BVH structure. Further, the apparatus may allocate the BVH structure into a first BVH section including a plurality of first nodes and a second BVH section including a plurality of second nodes. The apparatus may also store first data associated with the plurality of first nodes in the GMEM and second data associated with the plurality of first nodes and the plurality of second nodes in a system memory.Type: GrantFiled: February 4, 2022Date of Patent: February 28, 2023Assignee: QUALCOMM IncorporatedInventors: Adimulam Ramesh Babu, Srihari Babu Alla, David Kirk McAllister
-
Patent number: 9607407Abstract: A method, in one embodiment, can include performing difference transformation of image samples. In addition, the method can also include performing length selection. Furthermore; the method can include performing packing that includes utilizing varying sized bit fields to produce a compressed representation.Type: GrantFiled: December 31, 2012Date of Patent: March 28, 2017Assignee: NVIDIA CORPORATIONInventors: Jonathan Dunaisky, David Kirk McAllister, William Craig McKnight
-
Patent number: 9530189Abstract: A method for compressing framebuffer data is presented. The method includes determining a reduction ratio for framebuffer data in a tile including multiple samples. The reduction ratio determined is independent of the sampling mode, where the sampling mode is the number of samples within each pixel in the tile. The method further includes comparing a first portion of the framebuffer data for each of the multiple samples to determine an equality comparison result and also comparing a second portion of the framebuffer data for each one of the multiple samples to compute per-channel differences for each one of the multiple samples and testing the per-channel differences against a threshold value to determine a threshold comparison result. Finally, the method comprises compressing the framebuffer data for the tile based on the reduction ratio, the equality comparison result and the threshold comparison result to produce output framebuffer data for the tile.Type: GrantFiled: December 27, 2012Date of Patent: December 27, 2016Assignee: NVIDIA CORPORATIONInventors: Jonathan Dunaisky, David Kirk McAllister, Steven E. Molnar, Narayan Kulshrestha, Rui Bastos, Joseph Detmer, William Craig McKnight
-
Patent number: 9406149Abstract: A system and method are described for compressing image data using a combination of compression methods. Compression method combinations are provided to compress image data of a particular frame buffer format and antialiasing mode. Each method in the compression method combination is tried in turn to compress the image data in a tile. The best method that succeeded in compressing the image data is encoded in the compression bit state associated with the tile. Together, the compression bits, the compression method combination, and the frame buffer format provide sufficient information to decompress a tile.Type: GrantFiled: October 7, 2010Date of Patent: August 2, 2016Assignee: NVIDIA CorporationInventors: David Kirk McAllister, Narayan Kulshrestha, Steven E. Molnar
-
Patent number: 8872824Abstract: A system, method, and computer program product are provided for performing shadowing utilizing shadow maps and ray tracing. In operation, one or more shadow maps are rendered for at least one light source. Additionally, low confidence pixels associated with the one or more shadow maps are determined. Furthermore, shadow rays associated with the low confidence pixels are traced.Type: GrantFiled: March 3, 2010Date of Patent: October 28, 2014Assignee: NVIDIA CorporationInventors: Michael Robert Phillips, David Patrick Luebke, Jonathan Michael Cohen, Peter Schuyler Shirley, David Kirk McAllister
-
Patent number: 8862823Abstract: One embodiment of the present invention sets forth a compression status cache configured to store compression information for blocks of memory stored within an external memory. A data cache unit is configured to request, in response to a cache miss, compressed data from the external memory based on compression information stored in the compression status bit cache. The compression status for active buffers is dynamically swapped into the compression status cache as needed. Different compression formats may be specified for one or more tiles within an active buffer. One advantage of the disclosed compression status cache is that a lame amount of attached memory may be allocated as compressible memory blocks, without incurring a corresponding die area cost because a portion of the compression status stored off chip in attached memory is cached in the compression status cache.Type: GrantFiled: December 19, 2008Date of Patent: October 14, 2014Assignee: NVIDIA CorporationInventors: David B. Glasco, Cass W. Everitt, David Kirk Mcallister, Emmett M. Kilgariff, George R. Lynch, James Roberts, Karan Mehra, Patrick R. Marchand, Peter B. Holmqvist, Steven E. Molnar
-
Publication number: 20140184612Abstract: A method, in one embodiment, can include performing difference transformation of image samples. In addition, the method can also include performing length selection. Furthermore; the method can include performing packing that includes utilizing varying sized bit fields to produce a compressed representation.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicant: NVIDIA CORPORATIONInventors: Jonathan Dunaisky, David Kirk McAllister, Craig McKnight
-
Patent number: 8605104Abstract: One embodiment of the present invention sets forth a technique for compressing color data. Color data for a tile including multiple samples is compressed based on an equality comparison and a threshold comparison based on a programmable threshold value. The equality comparison is performed on a first portion of the color data that includes at least exponent and sign fields of floating point format values or high order bits of integer format values. The threshold comparison is performed on a second portion of the color data that includes mantissa fields of floating point format values or low order bits of integer format values. The equality comparison and threshold comparison are used to select either computed averages of the pixel components or the original color data as the output color data for the tile. When the threshold is set to zero, only tiles that can be compressed without loss are compressed.Type: GrantFiled: December 31, 2009Date of Patent: December 10, 2013Assignee: NVIDIA CorporationInventors: David Kirk McAllister, Steven E. Molnar, Narayan Kulshrestha