Abstract: A method of implementing a mask load or mask store instruction by a processor is provided. The method may include receiving the mask load or mask store instruction, a location of a memory operand and a location of corresponding mask bits associated with the memory operand, breaking the received memory operand into a plurality of sub-operands and executing the mask load or mask store instruction on each of the plurality of sub-operands using a fastpath operation or using microcode, wherein the respective mask load or mask store instruction loads or stores each of the plurality of sub-operands based upon the corresponding mask bits.

Abstract: A method of implementing a mask load or mask store instruction by a processor is provided. The method may include receiving the mask load or mask store instruction, a location of a memory operand and a location of corresponding mask bits associated with the memory operand, breaking the received memory operand into a plurality of sub-operands and executing the mask load or mask store instruction on each of the plurality of sub-operands using a fastpath operation or using microcode, wherein the respective mask load or mask store instruction loads or stores each of the plurality of sub-operands based upon the corresponding mask bits.

Abstract: An address generation unit (AGU) including a single adder and a recycling path. The recycling AGU may receive a plurality of operands at a first and at a second selection device to perform a first address generation operation. The adder may sum a portion of the operands to generate an output sum. Then, the output sum may be recycled back to the first selection device via the recycle path. The sum that is output from the adder may be recycled back to the first selection device one or more times via the recycle path depending on whether the first address generation operation requires one or more additional operands to be added to generate a corresponding address. Since the recycling AGU includes only a single adder, it may reduce the hardware necessary to perform the multiple computations that are typically required in an address generation operation without adversely affecting performance.