Patents by Inventor David Kruckemyer
David Kruckemyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118726Abstract: A die-to-die (D2D) interface between chiplets of a system on a chip (SoC) in which each of the chiplets are subdivided into slices. The D2D interface includes a transmission interface coupled between first and second chiplets, which includes a first transmission path for a first slice and a second transmission path for a second slice. The first chiplet includes receive circuitry which further includes a write interface and a read interface. The write interface stores data received from the first transmission path into a first FIFO using a first clock signal received via the first transmission path, and stores data received from the second transmission path into a second FIFO using a second clock signal received via the second transmission path. The read interface reads data stored in the first and second FIFOs using the first clock signal. The first and second transmission paths may be subject to different delays.Type: ApplicationFiled: July 7, 2023Publication date: April 11, 2024Inventors: David A. Kruckemyer, John G. Favor, Kelvin D. Goveas
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Publication number: 20230079078Abstract: In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.Type: ApplicationFiled: November 21, 2022Publication date: March 16, 2023Applicant: ARTERIS, INC.Inventors: David A. KRUCKEMYER, Craig Stephen FORREST
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Patent number: 11507510Abstract: In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.Type: GrantFiled: December 28, 2018Date of Patent: November 22, 2022Assignee: Arteris, Inc.Inventors: Craig Stephen Forrest, David A. Kruckemyer
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Patent number: 11237965Abstract: A cache coherent system includes a directory with more than one snoop filter, each of which stores information in a different set of snoop filter entries. Each snoop filter is associated with a subset of all caching agents within the system. Each snoop filter uses an algorithm chosen for best performance on the caching agents associated with the snoop filter. The number of snoop filter entries in each snoop filter is primarily chosen based on the caching capacity of just the caching agents associated with the snoop filter. The type of information stored in each snoop filter entry of each snoop filter is chosen to meet the desired filtering function of the specific snoop filter.Type: GrantFiled: December 31, 2014Date of Patent: February 1, 2022Assignee: ARTERIS, INC.Inventors: Craig Stephen Forrest, David A. Kruckemyer
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Patent number: 11080191Abstract: A cache coherent system includes a directory with more than one snoop filter, each of which stores information in a different set of snoop filter entries. Each snoop filter is associated with a subset of all caching agents within the system. Each snoop filter uses an algorithm chosen for best performance on the caching agents associated with the snoop filter. The number of snoop filter entries in each snoop filter is primarily chosen based on the caching capacity of just the caching agents associated with the snoop filter. The type of information stored in each snoop filter entry of each snoop filter is chosen to meet the desired filtering function of the specific snoop filter.Type: GrantFiled: March 18, 2020Date of Patent: August 3, 2021Assignee: ARTERIS, INC.Inventors: Craig Stephen Forrest, David A. Kruckemyer
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Publication number: 20200218657Abstract: A cache coherent system includes a directory with more than one snoop filter, each of which stores information in a different set of snoop filter entries. Each snoop filter is associated with a subset of all caching agents within the system. Each snoop filter uses an algorithm chosen for best performance on the caching agents associated with the snoop filter. The number of snoop filter entries in each snoop filter is primarily chosen based on the caching capacity of just the caching agents associated with the snoop filter. The type of information stored in each snoop filter entry of each snoop filter is chosen to meet the desired filtering function of the specific snoop filter.Type: ApplicationFiled: March 18, 2020Publication date: July 9, 2020Applicant: ARTERIS, INC.Inventors: Craig Stephen FORREST, David A. KRUCKEMYER
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Publication number: 20190129852Abstract: In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.Type: ApplicationFiled: December 28, 2018Publication date: May 2, 2019Applicant: Arteris, Inc.Inventors: Craig Stephen FORREST, David A. KRUCKEMYER
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Patent number: 10255183Abstract: In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.Type: GrantFiled: May 23, 2017Date of Patent: April 9, 2019Assignee: ARTERIS, Inc.Inventors: Craig Stephen Forrest, David A. Kruckemyer
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Patent number: 10133671Abstract: A system and method are disclosed that include a bridge that translates non-coherent transactions, which are received from a non-coherent subsystem, into one or more coherent transactions to be issued to a coherent subsystem. The bridge also buffers data coherently in an internal cache, also known as a proxy cache, based on certain attributes of the non-coherent transaction. The invention may be applied to any cache, which receives read and write transactions that become coherent transactions.Type: GrantFiled: December 30, 2016Date of Patent: November 20, 2018Assignee: ARTERIS, Inc.Inventors: David A Kruckemyer, Craig Stephen Forrest
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Publication number: 20170322883Abstract: In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.Type: ApplicationFiled: May 23, 2017Publication date: November 9, 2017Applicant: Arteris, Inc.Inventors: Craig Stephen Forrest, David A. Kruckemyer
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Patent number: 9807025Abstract: A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).Type: GrantFiled: August 2, 2016Date of Patent: October 31, 2017Assignee: Hewlett Packard Enterprise Development LPInventors: Randal G. Martin, Steven C. Miller, Mark D. Stadler, David A. Kruckemyer
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Publication number: 20170255558Abstract: The invention involves isolating a cache coherence controller from agents or units. The term unit as used herein may refer to one or more circuits, components, registers, processors, software subroutines, or any combination thereof. The separate units communicate with each other and are logically coupled.Type: ApplicationFiled: May 23, 2017Publication date: September 7, 2017Applicant: Arteris, Inc.Inventors: Craig Stephen Forrest, David A. Kruckemyer
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Publication number: 20170192890Abstract: A system and method are disclosed that include a bridge that translates non-coherent transactions, which are received from a non-coherent subsystem, into one or more coherent transactions to be issued to a coherent subsystem. The bridge also buffers data coherently in an internal cache, also known as a proxy cache, based on certain attributes of the non-coherent transaction. The invention may be applied to any cache, which receives read and write transactions that become coherent transactions.Type: ApplicationFiled: December 30, 2016Publication date: July 6, 2017Applicant: Arteris, Inc.Inventors: David A Kruckemyer, Craig Stephen Forrest
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Patent number: 9652391Abstract: Compression of address bits within a cache coherent subsystem of a chip is performed, enabling a cache coherent subsystem to avoid transmitting, storing, and operating upon unnecessary address information. Compression is performed according to any appropriate lossless algorithm, such as discarding of bits or code book lookup. The algorithm may be chosen according to constraints on logic delay and silicon area. An algorithm for minimum area would use a number of bits equal to the rounded up binary logarithm of the sum of all addresses of all memory regions. A configuration tool generates a logic description of the compression algorithm. The algorithm may be chosen automatically by the configuration tool. Decompression may be performed on addresses exiting the coherent subsystem.Type: GrantFiled: December 30, 2015Date of Patent: May 16, 2017Assignee: ARTERIS, Inc.Inventors: David A. Kruckemyer, Craig Stephen Forrest
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Publication number: 20170024320Abstract: A system and method are disclosed for multiple coherent caches supporting agents that use different, incompatible coherence models. Compatibility is implemented by translators that accept coherency requests and snoop responses from an agent and accept snoop requests and coherency responses from a coherence controller. The translators issue corresponding coherency requests and snoop responses to the coherence controller and issue corresponding coherency responses and snoop requests to the agent. Interaction between translators and the coherence controller accord with a generic coherence model, which may be a subset, superset, or partially inclusive of features of any native coherence model. A generic coherence protocol may include binary values for each of characteristics: valid or invalid, owned or non-owned, unique or shared, and clean or dirty.Type: ApplicationFiled: December 15, 2015Publication date: January 26, 2017Applicant: Arteris, Inc.Inventors: Craig Stephen FORREST, David A. KRUCKEMYER
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Patent number: 9542316Abstract: A system and method are disclosed for multiple coherent caches supporting agents that use different, incompatible coherence models. Compatibility is implemented by translators that accept coherency requests and snoop responses from an agent and accept snoop requests and coherency responses from a coherence controller. The translators issue corresponding coherency requests and snoop responses to the coherence controller and issue corresponding coherency responses and snoop requests to the agent. Interaction between translators and the coherence controller accord with a generic coherence model, which may be a subset, superset, or partially inclusive of features of any native coherence model. A generic coherence protocol may include binary values for each of characteristics: valid or invalid, owned or non-owned, unique or shared, and clean or dirty.Type: GrantFiled: December 15, 2015Date of Patent: January 10, 2017Assignee: ARTERIS, INC.Inventors: Craig Stephen Forrest, David A. Kruckemyer
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Publication number: 20160344644Abstract: A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).Type: ApplicationFiled: August 2, 2016Publication date: November 24, 2016Inventors: Randal G. Martin, Steven C. Miller, Mark D. Stadler, David A. Kruckemyer
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Patent number: 9432299Abstract: A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).Type: GrantFiled: March 2, 2015Date of Patent: August 30, 2016Assignee: Silicon Graphics International Corp.Inventors: Randal G. Martin, Steven C. Miller, Mark D. Stadler, David A. Kruckemyer
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Publication number: 20160188473Abstract: Compression of address bits within a cache coherent subsystem of a chip is performed, enabling a cache coherent subsystem to avoid transmitting, storing, and operating upon unnecessary address information. Compression is performed according to any appropriate lossless algorithm, such as discarding of bits or code book lookup. The algorithm may be chosen according to constraints on logic delay and silicon area. An algorithm for minimum area would use a number of bits equal to the rounded up binary logarithm of the sum of all addresses of all memory regions. A configuration tool generates a logic description of the compression algorithm. The algorithm may be chosen automatically by the configuration tool. Decompression may be performed on addresses exiting the coherent subsystem.Type: ApplicationFiled: December 30, 2015Publication date: June 30, 2016Applicant: Arteris, Inc.Inventors: David A. KRUCKEMYER, Craig Stephen FORREST
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Publication number: 20160188471Abstract: A cache coherent system includes a directory with more than one snoop filter, each of which stores information in a different set of snoop filter entries. Each snoop filter is associated with a subset of all caching agents within the system. Each snoop filter uses an algorithm chosen for best performance on the caching agents associated with the snoop filter. The number of snoop filter entries in each snoop filter is primarily chosen based on the caching capacity of just the caching agents associated with the snoop filter. The type of information stored in each snoop filter entry of each snoop filter is chosen to meet the desired filtering function of the specific snoop filter.Type: ApplicationFiled: December 31, 2014Publication date: June 30, 2016Inventors: Craig Stephen Forrest, David A. Kruckemyer