Abstract: Broadly speaking, embodiments of the present techniques provide haptic button assemblies in which the haptic button has a low profile while still providing a satisfying tactile response or sensation to a user. Advantageously, the haptic button assemblies may have a profile that, for example, enables the assembly to be incorporated into the free space along an edge of a portable computing device. The haptic assemblies may, for example, be arranged to move the button perpendicularly with respect to the edge of the device.

Abstract: Broadly speaking, embodiments of the present techniques provide haptic button assemblies in which the haptic button has a low profile while still providing a satisfying tactile response or sensation to a user. Advantageously, the haptic button assemblies may have a profile that, for example, enables the assembly to be incorporated into the free space along an edge of a portable computing device. The haptic assemblies may, for example, be arranged to move the button perpendicularly with respect to the edge of the device.

Abstract: Arrangements and methods for a program-read-erase memory using ReRAM cells is disclosed. The memory includes an array of pristine ReRAM cells. A first digital symbol is encoded in the memory by partially forming cells, while the opposite digital value is encoded in pristine cells. As part of a read process, all cells are subject to partial formation voltage which erases all data as it is being read. ReRAM memories used in this manner are advantageously usable to store challenges for interrogating PUFs for recovery of PUF-generated encryption keys.

Abstract: Broadly speaking, embodiments of the present techniques provide haptic button assemblies in which the haptic button has a low profile while still providing a satisfying tactile response or sensation to a user. Advantageously, the haptic button assemblies may have a profile that, for example, enables the assembly to be incorporated into the free space along an edge of a portable computing device. The haptic assemblies may, for example, be arranged to move the button perpendicularly with respect to the edge of the device.

Abstract: A client-based solution for seamless access to applications across networks is agnostic to the inter-network mix of application architectures with or without IMS. In one embodiment, the presence of an added layer of intelligence effectively traverses and is agnostic to the various standards layers.

Abstract: A client-based solution for seamless access to applications across networks is agnostic to the inter-network mix of application architectures with or without IMS. In one embodiment, an application client registers in either an integrated mode or a standalone mode based whether an application availability notification is received within a predetermined period of time.

Abstract: A system and method for providing integrated voice quality measurements for wireless networks, based on actual calls made by end devices, are provided. The system includes a plurality of end devices, each of which includes an algorithm for determining voice quality data; an over-the-air server configured to enable voice quality reporting in the end devices; a messaging server configured to receive voice quality reports from the end devices; a voice quality server configured to receive the voice quality reports from the messaging server and consolidate the voice quality reports; and a call data record server configured to combine call records and the consolidated voice quality reports.

Abstract: Several embodiments of an IMS communications network are disclosed. In one embodiment, the network comprises a plurality of dispatch application servers (DAS), an S-CSCF, and an event notification server. The S-CSCF is adapted to receive an IMS registration request from a dispatch client, authenticate the registration request, send a registration confirmation to the dispatch client, and send a notification indicating the registration of the dispatch client to an event notification server. The event notification server is adapted to receive the notification from the S-CSCF, select a DAS, and send a notification to the selected DAS indicating an assignment to provide dispatch service to the dispatch client. In another embodiment, the registration notification to the event notification server is sent from the dispatch client, instead of the S-CSCF.

Abstract: A non-volatile memory device and method for manufacture and programing which does not require a control gate for the programing or erasure of the device. The memory device is comprised of two wells with the opposite conductivity type of the semiconductor body. In one of the wells is a source and drain well of the same conductivity type as of the body. A oxide is formed on the surface of the body on which a floating gate is formed. Specific voltages are applied to the source, drain, first well and second well region to program, erase and read the memory device.

Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.

Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.

Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.

Abstract: Methods and apparatus, including computer program products, for a one or multiple-times programmable memory device. A semiconductor may include an active region of a substrate, a thin oxide layer over a substrate, a first and second polysilicon layer, and a first and second metal layer. The first polysilicon layer may have a floating gate, the active region may be substantially perpendicular to the floating gate, and the second polysilicon layer may include a control gate. The first metal layer may include a bit line connected to a first n-diffused region, where the bit line is substantially perpendicular to the floating gate. The second metal layer may include a word line and source line. The word line may be connected to the control gate, and the source line may be connected to a second n-diffused region. The thin gate oxide may have a thickness between 65 and 75 angstroms.

Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.

Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.

Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.

Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.

Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.

Abstract: Methods and apparatus, including computer program products, for a one or multiple-times programmable memory device. A semiconductor may include an active region of a substrate, a thin oxide layer over a substrate, a first and second polysilicon layer, and a first and second metal layer. The first polysilicon layer may have a floating gate, the active region may be substantially perpendicular to the floating gate, and the second polysilicon layer may include a control gate. The first metal layer may include a bit line connected to a first n-diffused region, where the bit line is substantially perpendicular to the floating gate. The second metal layer may include a word line and source line. The word line may be connected to the control gate, and the source line may be connected to a second n-diffused region. The thin gate oxide may have a thickness between 65 and 75 angstroms.

Abstract: A client-based solution for seamless access to applications across networks is agnostic to the inter-network mix of application architectures with or without IMS. In one embodiment, the presence of an added layer of intelligence effectively traverses and is agnostic to the various standards layers.