Patents by Inventor David Kuan-Yu Liu
David Kuan-Yu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230291581Abstract: Arrangements and methods for a program-read-erase memory using ReRAM cells is disclosed. The memory includes an array of pristine ReRAM cells. A first digital symbol is encoded in the memory by partially forming cells, while the opposite digital value is encoded in pristine cells. As part of a read process, all cells are subject to partial formation voltage which erases all data as it is being read. ReRAM memories used in this manner are advantageously usable to store challenges for interrogating PUFs for recovery of PUF-generated encryption keys.Type: ApplicationFiled: March 13, 2023Publication date: September 14, 2023Inventors: Bertrand F. Cambou, Ian Burke, Taylor Begay, David Kuan-Yu Liu
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Patent number: 7944750Abstract: A non-volatile memory device and method for manufacture and programing which does not require a control gate for the programing or erasure of the device. The memory device is comprised of two wells with the opposite conductivity type of the semiconductor body. In one of the wells is a source and drain well of the same conductivity type as of the body. A oxide is formed on the surface of the body on which a floating gate is formed. Specific voltages are applied to the source, drain, first well and second well region to program, erase and read the memory device.Type: GrantFiled: October 22, 2008Date of Patent: May 17, 2011Assignee: Maxim Integrated Products, Inc.Inventors: Albert Bergemont, David Kuan-Yu Liu, Venkatraman Prabhakar, Sridevi Rajagopalan Schmidt
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Patent number: 7835184Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.Type: GrantFiled: September 18, 2008Date of Patent: November 16, 2010Assignee: Maxim Integrated Products, Inc.Inventors: Nirmal Ratnakumar, Venkatraman Prabhakar, David Kuan-Yu Liu
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Patent number: 7835186Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.Type: GrantFiled: July 7, 2008Date of Patent: November 16, 2010Assignee: Maxim Integrated Products, Inc.Inventors: Nirmal Ratnakumar, Venkatraman Prabhakar, David Kuan-Yu Liu
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Patent number: 7791955Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.Type: GrantFiled: July 7, 2008Date of Patent: September 7, 2010Assignee: Maxim Integrated Products, Inc.Inventors: Nirmal Ratnakumar, Venkatraman Prabhakar, David Kuan-Yu Liu
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Patent number: 7535758Abstract: Methods and apparatus, including computer program products, for a one or multiple-times programmable memory device. A semiconductor may include an active region of a substrate, a thin oxide layer over a substrate, a first and second polysilicon layer, and a first and second metal layer. The first polysilicon layer may have a floating gate, the active region may be substantially perpendicular to the floating gate, and the second polysilicon layer may include a control gate. The first metal layer may include a bit line connected to a first n-diffused region, where the bit line is substantially perpendicular to the floating gate. The second metal layer may include a word line and source line. The word line may be connected to the control gate, and the source line may be connected to a second n-diffused region. The thin gate oxide may have a thickness between 65 and 75 angstroms.Type: GrantFiled: February 6, 2007Date of Patent: May 19, 2009Assignee: Maxim Integrated Products, Inc.Inventors: Albert Bergemont, David Kuan-Yu Liu, Venkatraman Prabhakar
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Publication number: 20090014772Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.Type: ApplicationFiled: September 18, 2008Publication date: January 15, 2009Applicant: Maxim Integrated Products, Inc.Inventors: Nirmal Ratnakumar, Venkatraman Prabhakar, David Kuan-Yu Liu
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Publication number: 20080273392Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.Type: ApplicationFiled: July 7, 2008Publication date: November 6, 2008Applicant: MAXIM INTEGRATED PRODUCTS, INC.Inventors: Nirmal Ratnakumar, Venkatraman Prabhakar, David Kuan-Yu Liu
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Publication number: 20080273401Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.Type: ApplicationFiled: July 7, 2008Publication date: November 6, 2008Applicant: MAXIM INTEGRATED PRODUCTS, INC.Inventors: Nirmal Ratnakumar, Venkatraman Prabhakar, David Kuan-Yu Liu
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Patent number: 7436710Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.Type: GrantFiled: March 12, 2007Date of Patent: October 14, 2008Assignee: Maxim Integrated Products, Inc.Inventors: Nirmal Ratnakumar, Venkatraman Prabhakar, David Kuan-Yu Liu
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Publication number: 20080225601Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line.Type: ApplicationFiled: March 12, 2007Publication date: September 18, 2008Applicant: MAXIM INTEGRATED PRODUCTS, INC.Inventors: Nirmal Ratnakumar, Venkatraman Prabhakar, David Kuan-Yu Liu
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Publication number: 20080186773Abstract: Methods and apparatus, including computer program products, for a one or multiple-times programmable memory device. A semiconductor may include an active region of a substrate, a thin oxide layer over a substrate, a first and second polysilicon layer, and a first and second metal layer. The first polysilicon layer may have a floating gate, the active region may be substantially perpendicular to the floating gate, and the second polysilicon layer may include a control gate. The first metal layer may include a bit line connected to a first n-diffused region, where the bit line is substantially perpendicular to the floating gate. The second metal layer may include a word line and source line. The word line may be connected to the control gate, and the source line may be connected to a second n-diffused region. The thin gate oxide may have a thickness between 65 and 75 angstroms.Type: ApplicationFiled: February 6, 2007Publication date: August 7, 2008Inventors: Albert Bergemont, David Kuan-Yu Liu, Venkatraman Prabhakar
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Patent number: 7301194Abstract: A nonvolatile EEPROM cell having a double poly arrangement provides stored data without sense amplifiers, thereby reducing power requirements. The EEPROM cell has a floating gate in a first poly layer, and a control gate overlapping the floating gate in a second poly layer. This configuration allows for an area-efficient layout that is easily shrinkable as compared to prior art memory cells. In addition, stacking the control and floating gates results in higher capacitive coupling. The EEPROM cell also includes an access gate, a tunnel capacitor, and at least one inverter. In some embodiments, the EEPROM cell can be advantageously used to configure programmable logic without need for a conloading step.Type: GrantFiled: November 15, 2004Date of Patent: November 27, 2007Assignee: Xilinx, Inc.Inventors: Sunhom Paak, David Kuan-Yu Liu, Anders T. Dejenfelt, Cyrus Chang, Qi Lin, Phillip A. Young
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Patent number: 7091077Abstract: Polysilicon or other material is directionally trimmed using two layers of photoresist and a photoresist etching process, such as ashing. A first layer of photoresist is patterned on a wafer. Portions of the first patterned photoresist are covered with a second layer of photoresist. The photoresist is trimmed to reduce the size of the exposed portions of the first patterned photoresist without reducing the size of the covered portions of the first patterned photoresist. The second layer of photoresist is removed. The selectively etched patterned first layer of photoresist is used as a process mask to define a structure in the underlying material. In a particular embodiment, the second photoresist covers endcap portions of gate photoresist. Directional trimming reduces the width of a polysilicon gate structure (i.e. gate length) over an active area of an FET, without reducing the length of original first patterned photoresist.Type: GrantFiled: June 7, 2005Date of Patent: August 15, 2006Assignee: Xilinx, Inc.Inventors: David Kuan-Yu Liu, Jonathan Cheang-Whang Chang
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Patent number: 6711063Abstract: An EEPROM memory cell array architecture (50) that substantially eliminates leakage current to allow for reading memory cells (20) in a memory cell array of, for example, a CPLD at lower voltages than are possible with prior art architectures, thereby facilitating development of low voltage applications. This is accomplished by associating each wordline of the memory cell array with a ground transistor (26). On one embodiment, the ground transistor (26) can be a high voltage transistor, in which case the same high voltage control signal can control both the ground transistor (26) and the memory cell=s read transistor (32). In another embodiment, the ground transistor (26) is a low voltage transistor controlled by a separate low voltage control signal.Type: GrantFiled: October 3, 2002Date of Patent: March 23, 2004Assignee: Xilinx, Inc.Inventors: Anders T. Dejenfelt, David Kuan-Yu Liu
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Patent number: 6624026Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A pair of sources for a pair of cells on adjacent word lines each acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor of one cell operates as a charge injector for the other cell. The charge injector provides carriers for substrate hot carrier injection onto a floating gate.Type: GrantFiled: March 21, 2000Date of Patent: September 23, 2003Assignee: Programmable Silicon SolutionsInventors: David Kuan-Yu Liu, Ting-Wah Wong, Kelvin Yupak Hui
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Patent number: 6127225Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector provides electrons for substrate hot electron injection of electrons onto the floating gate for programming. The cell depletion/inversion region may be extended by forming a capacitor as an extension of the control gate over the substrate between the source and channel of said sense transistor.Type: GrantFiled: December 10, 1999Date of Patent: October 3, 2000Assignee: Programmable Silicon SolutionsInventors: David Kuan-Yu Liu, Ting-wah Wong
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Patent number: 6088263Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A pair of sources for a pair of cells on adjacent word lines each acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor of one cell operates as a charge injector for the other cell. The charge injector provides carriers for substrate hot carrier injection onto a floating gate.Type: GrantFiled: November 15, 1999Date of Patent: July 11, 2000Assignee: Programmable Silicon SolutionsInventors: David Kuan-Yu Liu, Ting-Wah Wong, Kelvin Yupak Hui
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Patent number: 6027974Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector provides electrons for substrate hot electron injection of electrons onto the floating gate for programming. The cell depletion/inversion region may be extended by forming a capacitor as an extension of the control gate over the substrate between the source and channel of said sense transistor.Type: GrantFiled: November 25, 1998Date of Patent: February 22, 2000Assignee: Programmable Silicon SolutionsInventors: David Kuan-Yu Liu, Ting-wah Wong
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Patent number: 6026017Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A pair of sources for a pair of cells on adjacent word lines each acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor of one cell operates as a charge injector for the other cell. The charge injector provides carriers for substrate hot carrier injection onto a floating gate.Type: GrantFiled: November 10, 1998Date of Patent: February 15, 2000Assignee: Programmable Silicon SolutionsInventors: Ting-wah Wong, David Kuan-Yu Liu, Kelvin YuPak Hui