Patents by Inventor David Kudzuma
David Kudzuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6898343Abstract: A hybrid integration process for fabrication of an optical cross-connect switching apparatus. The switching element is based on the deflection of light beam in electro-optic materials by applying electric field across electrodes of an appropriate configuration. The integration process includes fabrication of a substrate (e.g. silicon substrate) with 2D imaging optics from polymeric materials (or silica), fabrication of the light deflecting element, and assembly of the deflecting element on the substrate with imaging optics. The fabrication of the light deflecting element includes fabrication of a LN (lithium niobate) block. The LN block assembled in an optical switching apparatus includes a two-dimensional waveguide formed on a surface of the LN block and an electrode on a surface of the LN block.Type: GrantFiled: August 17, 2001Date of Patent: May 24, 2005Assignee: Fujitsu LimitedInventors: Alexei Glebov, Michael Peters, Michael Lee, James Roman, David Kudzuma
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Publication number: 20030035614Abstract: A hybrid integration process for fabrication of an optical cross-connect switching apparatus. The switching element is based on the deflection of light beam in electro-optic materials by applying electric field across electrodes of an appropriate configuration. The integration process includes fabrication of a substrate (e.g. silicon substrate) with 2D imaging optics from polymeric materials (or silica), fabrication of the light deflecting element, and assembly of the deflecting element on the substrate with imaging optics. The fabrication of the light deflecting element includes fabrication of a LN (lithium niobate) block. The LN block assembled in an optical switching apparatus includes a two-dimensional waveguide formed on a surface of the LN block and an electrode on a surface of the LN block.Type: ApplicationFiled: August 17, 2001Publication date: February 20, 2003Inventors: Alexei Glebov, Michael Peters, Michael Lee, James Roman, David Kudzuma
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Patent number: 6102710Abstract: An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed through rigid segments and signals are routed through a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected.Type: GrantFiled: April 30, 1998Date of Patent: August 15, 2000Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Michael G. Peters, James J. Roman, Som S. Swamy, Wen-chou Vincent Wang, Larry L. Moresco, Teruo Murase
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Patent number: 5930890Abstract: An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.Type: GrantFiled: April 21, 1997Date of Patent: August 3, 1999Assignee: Fujitsu LimitedInventors: William T. Chou, Solomon I. Beilin, David A. Horine, David Kudzuma, Michael G. Lee, Larry Louis Moresco, Wen-chou Vincent Wang
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Patent number: 5854534Abstract: An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed though rigid segments and signals are routed though a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected.Type: GrantFiled: November 16, 1995Date of Patent: December 29, 1998Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Michael G. Peters, James J. Roman, Som S. Swamy, Wen-chou Vincent Wang, Larry L. Moresco, Teruo Murase
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Patent number: 5778529Abstract: A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.Type: GrantFiled: May 22, 1996Date of Patent: July 14, 1998Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Teruo Murase, Michael G. Peters, James J. Roman, Som S. Swamy, Wen-Chou Vincent Wang
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Patent number: 5722162Abstract: An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.Type: GrantFiled: October 12, 1995Date of Patent: March 3, 1998Assignee: Fujitsu LimitedInventors: William T. Chou, Solomon I. Beilin, David A. Horine, David Kudzuma, Michael G. Lee, Larry Louis Moresco, Wen-chou Vincent Wang
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Patent number: 5660957Abstract: Methods for pretreating patterned masks layers, such as photoresist masks, with electron-beam radiation for use in high temperature processes are disclosed. The electron-beam exposure deactivates compounds within the mask material which would ordinarily decompose and produce gasses within the photoresist layer. The gasses cause blistering in the untreated photoresist layer, which in turn degrades the dimensional integrity of the untreated layer.Type: GrantFiled: May 16, 1996Date of Patent: August 26, 1997Assignee: Fujitsu LimitedInventors: William T. Chou, Solomon I. Beilin, David Kudzuma, Wen-chou Vincent Wang
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Patent number: 5544017Abstract: A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.Type: GrantFiled: July 19, 1994Date of Patent: August 6, 1996Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Teruo Murase, Michael G. Peters, James J. Roman, Som S. Swamy, Wen-chou V. Wang
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Patent number: 5419038Abstract: A three dimensional thin-film interconnector is fabricated by depositing a dielectric layer onto the surface of a substrate, depositing a layer of conductive material onto the dielectric layer to form a signal plane, depositing a dielectric layer onto the surface of the signal plane, forming a plurality of through holes in the dielectric layer that extend to the signal plane, and filling the through holes with an electrically conductive material to form vias. The sequence of forming a signal plane, depositing a dielectric layer, forming a plurality of through holes, and filling the through holes is repeated until a predetermined number of signal planes and a predetermined arrangement of vias are obtained. The through holes are formed at locations in the dielectric layers corresponding to both predetermined electrical connections and the vias in a preceding dielectric layer. The signal planes are formed at different locations on the substrate.Type: GrantFiled: June 17, 1993Date of Patent: May 30, 1995Assignee: Fujitsu LimitedInventors: Wen-chou V. Wang, Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Michael G. Peters, James J. Roman, Som S. Swamy