Abstract: A circuit to control the slew rate of charging a capacitance using the capacitance is disclosed. An example circuit includes a regulator circuit to regulate a supply voltage during a normal operation mode of the circuit. A capacitance circuit is coupled to the regulator circuit. The regulator circuit is coupled to charge a capacitance between a first node and a second node of the capacitance circuit with a charge current. A slew rate control circuit is coupled to the regulator circuit and the capacitance circuit. The slew rate control circuit sets a slew rate of a voltage between the first and second nodes during a power up mode of the circuit.

Abstract: A temperature independent reference circuit includes first and second bipolar transistors with commonly coupled bases. First and second resistors are coupled in series between the emitter of the second bipolar transistor and ground. The first and second resistors have first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3 and TC2, respectively. The resistance values being such that a temperature coefficient of a difference between the base-emitter voltages of the first and second bipolar transistors, TC1, is substantially equal to TC2×(R2/(R1+R2))+TC3×(R1/(R1+R2)), resulting in a reference current flowing through each of the first and second bipolar transistors that is substantially constant over temperature. A third resistor coupled between a node and the collector of the second bipolar transistor has a value such that a reference voltage generated at the node is substantially constant over temperature.

Abstract: A circuit to discharge a capacitance between input terminals of a power system is disclosed. An example circuit includes a control circuit coupled to an input of a power system. The control circuit is coupled to detect whether an electrical energy source is coupled to an input of the power system. A switch is also included and is coupled to the control circuit and to the input of the power system. The control circuit is coupled to drive the switch in a first operating mode when the electrical energy source is coupled to the input of the power system. The control circuit is coupled to drive the switch in a second operating mode when the electrical energy source is uncoupled from the input of the power system. A capacitance coupled between input terminals of the input of the power system is discharged through the switch to a threshold voltage in less than a maximum period of time from when the electrical power source is uncoupled from the input terminals of the power system.

Abstract: An example controller includes a constant current control circuit and an integrator included in the constant current control circuit. The constant current control circuit is to be coupled to receive an input current sense signal, an input voltage sense signal, and an output voltage sense signal. The control circuit is adapted to regulate an output current of a power supply by generating a control signal to control switching of a switch. The integrator is coupled to integrate the input current sense signal during a switching period of the control signal to generate an integrated signal representative of a charge taken from an input voltage source of the power supply. The constant current control circuit is adapted to control the switching of the switch such that the integrated signal is proportional to a ratio of the output voltage sense signal to the input voltage sense signal.

Abstract: A retaining and adjusting device is provided for displaceable furniture parts, in particular for a leaf that is hinged so that it can pivot horizontally on an item of furniture, e.g. for a leaf of an upper cupboard. The device includes at least one control lever, whose length can be adjusted and which can be hinged on the part, the length of the control level and/or the position of the bearing point of the control lever being adjustable when the furniture part is closed.

Abstract: A computer readable storage medium includes executable instructions to assess system cache resources, inter-process communication requirements and staging requirements to divide an extract, transform, load (ETL) dataflow task into a plurality of sub-tasks. The sub-tasks are then executed in parallel on distributed resources.

Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Abstract: The invention relates to a retaining and adjusting device for displaceable furniture parts, in particular for a leaf that is hinged so that it can pivot horizontally on an item of furniture, e.g. for a leaf of an upper cupboard. Said device comprises at least one control lever, whose length can be adjusted and which can be hinged on the part, the length of the control level and/or the position of the bearing point of the control lever being adjustable when the furniture part is closed.

Abstract: An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

Abstract: A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

Abstract: A signal transmission mechanism between a wireless microphone and a receiver comprises a receiver, a wireless microphone and a microphone transmitter. A recess is formed on a surface of the receiver, wherein a plurality of electric contact points is disposed within the recess for facilitating an electric contact with either the wireless microphone or the microphone transmitter. The wireless microphone and the microphone transmitter respectively have extended rear ends capable of being coupled with the recess of the receiver and respectively have electric contact points, whereby the electric contact points of the wireless microphone or the microphone transmitter will be in electric contact with a corresponding set of the electric contact points of the receiver for frequency alignment. Since the frequency alignment is achieved through direct contact, the process of alignment will be quick, precise and free from external radio disturbances.

Abstract: A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.

Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Abstract: An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.

Abstract: An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

Abstract: A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

Abstract: A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and transitional delay from a first (low) voltage net source through the level converter and to a second (higher) voltage net sink. Then, inefficient level converters are eliminated. Level converters with fanin cones below a selected minimum cone size are deleted and low voltage sources to the deleted level converter reverted. Higher voltage level circuit elements receiving inputs from multiple level converters are replaced with equivalent low voltage circuit elements. Low voltage buffer driving level converters are both replaced by a single said level converter.

Abstract: A process and system are provided for representing object interactions, by means of a sequence diagram or the like, wherein the object interactions are recovered from source code written in Java or other object-oriented programming language. Initially, a Method Information Parser determines the respective methods declared inside the source code and extracts their names. A Method Detail Parser then extracts the method calls to other objects within a method, to resolve each complex method call into multiple lines of single method calls. Information derived from the multiple lines of single method calls is then used to generate the sequence diagram.