Abstract: Hydroscopic polymer gels can be formed by applying a polymer to a surface and allowing water to be sequestered from the atmosphere into the polymer. The polymer gels are formed using methods and compositions employing water soluble or water dispersible copolymers having: (i) a first monomer that is acidic and is capable of forming an anionic charge in the composition; (ii) a second monomer that is amphipathic; (iii) optionally, a third monomer that is hydrophobic; and (iv) optionally, a fourth monomer that that has a permanent cationic charge or that is capable of forming a cationic charge on protonation. The polymer gels are particularly substantive and effective at modifying surfaces such as glass and hydrophobic polymeric substrates to provide soap scum and soil resistance, and easier next time cleaning benefits.

Abstract: Incorporating dirt-attracting polycationic polymers, such as polyethyleneimines, into cleaning wipes, mop pads, and similar substrates, improves dirt pick-up and retards redeposition of the dirt back onto the cleaned surface. The polymers can be incorporated directly into the non-woven substrates or they can be formulated with a cleaning composition for use with the substrate. The substrate containing the dirt-attracting polycationic polymers can be employed to clean hard and soft surfaces. The presence of the dirt-attracting polycationic polymers also facilitates biocide release from the substrates.

Abstract: Incorporating dirt-attracting polycationic polymers, such as polyethyleneimines, into cleaning wipes, mop pads, and similar substrates, improves dirt pick-up and retards redeposition of the dirt back onto the cleaned surface. The polymers can be incorporated directly into the non-woven substrates or they can be formulated with a cleaning composition for use with the substrate. The substrate containing the dirt-attracting polycationic polymers can be employed to clean hard and soft surfaces. The presence of the dirt-attracting polycationic polymers also facilitates biocide release from the substrates.

Abstract: Incorporating dirt-attracting polycationic polymers, such as polyethyleneimines, into cleaning wipes, mop pads, and similar substrates, improves dirt pick-up and retards redeposition of the dirt back onto the cleaned surface. The polymers can be incorporated directly into the non-woven substrates or they can be formulated with a cleaning composition for use with the substrate. The substrate containing the dirt-attracting polycationic polymers can be employed to clean hard and soft surfaces. The presence of the dirt-attracting polycationic polymers also facilitates biocide release from the substrates.

Abstract: Improved savory snack food items include a nonsweet, sugar-based binder composition which adheres one or more toppings to a base portion of the snack. The binder does not undesirably alter the taste of snack food items and substantially reduces separation of toppings from the snack food items during production, packaging, shipping and, most importantly, during handling by the consumer. The binder also reduces transfer of oil and fat and powders to the hands of the consumer.

Abstract: Low oil potato chips are produced by washing potato slices with an aqueous solution and applying oil to the washed slices to at least partially coat the slices with oil. The oil-coated slices are blanched at a temperature of about 70.degree.-100.degree. C. (about 160.degree.-212.degree. F.), and then baked at a high temperature of at least about 200.degree. C. (about 390.degree. F.) but below the smoke point of the oil, to partially dry the slices to an aqueous moisture content of about 10-25 weight percent. The partially dried slices are further baked at a low temperature of about 145.degree.-160.degree. C. (about 290.degree.-320.degree. F.) to finish drying the slices to an aqueous moisture content of about 2 weight percent or less.

Abstract: An extruded, cross-cut snack food product and a method and apparatus for producing extruded, generally planar food products having ridges and valleys formed on opposite sides thereof, wherein the ridges and valleys on each side are parallel to each other, but are at an angle relative to the ridges and valleys on the opposite side. As a result, an extruded food product piece with unique texture, flavor and appearance is produced having substantial strength.

Abstract: A number of intelligent nodes (bus interface units-BIUs and memory control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Error-detection mechanisms deal with information flow occuring across area boundaries. Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error report lines (106, 108). If an error recurs the node at which the error exists initiates an error message which is received and repropagated on the error report lines by all nodes. The error message identifies the type of error and the node ID at which the error was detected. Confinement area isolation logic in a node isolates a faulty confinement area of which the node is a part, upon the condition that the node ID in an error report message identifies the node as a node which is a part of a faulty confinement area.

Abstract: A number of intelligent nodes (bus-interface units-BIUs and memory-control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error-report lines (106, 108). Processor modules (110) and memory modules (112) are each connected to a node which controls access to a common memory bus (107). Each node includes means (a married bit-170 and a shadow bit-172) for marrying modules in pairs such that each module in the pair tracks the operations directed to the module pair, and each module in the pair alternates with the other module in the handling of requests or replies. Each node registers the ID of the other node in a spouse ID register.

Abstract: A number of intelligent bus interface units (100) are provided in a matrix of orthogonal lines interconnecting processor modules (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding control lines; and memory buses (107) with corresponding control lines (108). At the intersection of these lines is a bus interface unit node (100). The bus interface units function to pass memory requests from a processor module to a memory module attached to an MCU node and to pass any data associated with the requests. The memory bus is a packet-oriented bus. Accesses are handled by means of a series of messages transmitted by message generator (417) in accordance with a specific control protocol. Packets comprising one or more bus transmission slots are issued sequentially and contiguously. Each slot in a packet includes an opcode, address, data, control, and parity-check bits. Write-request packets and read-request packets are issued to the memory-control unit.

Abstract: An arbitration mechanism comprising a request FIFO (408) for storing ones and zeros corresponding to received requests in the order that they are made. A one indicates that the request was made by the module in which the FIFO is located, and a zero indicates that the request was made by one of a number of other similar modules. The request status information from the other modules is received over signal lines (411) connected between the modules. This logic separates multiple requests into time-ordered slots, such that all requests in a particular time slot may be serviced before any requests in the next time slot. A store (409) stores a unique logical module number. An arbiter (410) examines this logical number bit-by-bit in successive cycles and places a one in a grant queue (412) upon the condition that the bit examined in a particular cycle is a zero and signals this condition over the signal lines.

Abstract: A number of intelligent crossbar switches (100) are provided in a matrix of orthogonal lines interconnecting processor (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding error-reporting lines (106); and memory buses (107) with corresponding error-reporting lines (108). At the intersection of these lines is a crossbar switch node (100). The crossbar switches function to pass memory requests from a processor to a memory module attached to an MCU node and to pass any data associated with the requests. The system is organized into confinement areas at the boundaries of which are positioned error-detection mechanisms to deal with information flow occurring across area boundaries. Each crossbar switch and MCU node has means for the logging and signaling of errors to other nodes. Means are provided to reconfigure the system to reroute traffic around the confinement area at fault and for restarting system operation in a possibly degraded mode.

Abstract: An execution unit which is part of a general-purpose microprocessor, partitioned between two integrated circuit chips, with the execution unit on one chip and an instruction unit on another chip. The execution unit provides the interface for accessing a main memory to thereby fetch data and macroinstructions for transfer to the instruction unit when requested to do so by the instruction unit. The execution unit receives arithmetic microinstructions in order to perform various arithmetic operations, and receives access-memory microinstructions in order to develop memory references from logical addresses received from the instruction unit. Arithmetic operations are performed by a data manipulation unit which contains registers and arithmetic capability, controlled by a math sequencer.

Abstract: A buffer utilizing MOS devices for coupling a computer input data line and a computer output data line to a single input/output port is disclosed. The buffer receives a control signal generated by computer port control means at the beginning of any buffer cycle when data is to be accepted by the buffer.

Abstract: An MOS digital computer incorporated on a single chip (monolithic structure) which includes a central processing unit (CPU), random-access memory (RAM), and a programmable read-only memory (PROM). A program counter is used to fetch instructions stored in the erasable PROM, and may also be used to fetch instructions from an external memory. The PROM may also be externally addressed for testing, or may be electrically isolated from the remainder of the computer to permit execution of external instructions for testing the CPU and RAM.