Patents by Inventor David L. Buster

David L. Buster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Partially etched dielectric film with conductive features
    Patent number: 7012017
    Abstract: Provided are partially etched dielectric films with raised conductive features. Also provided are methods for forming the raised conductive features in the dielectric films, which methods include partially etching the dielectric films.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: March 14, 2006
    Assignee: 3M Innovative Properties Company
    Inventors: Dennis M. Brunner, David L. Buster, Michael S. Graff, Daniel K. Luebbert, Nathan P. Kreutter, Rui Yang, Guoping Mao
  • Printed circuit substrate with controlled placement covercoat layer
    Patent number: 6720127
    Abstract: A covercoated base substrate, comprising a base substrate and a photoimageable covercoat layer having a lead portion extending beyond at least one, wherein the lead portion has a controlled offset distance from the edge, and a printed circuit made from such base substrate having at least one conductor including a trace and a lead wherein the covercoat has a lead portion covering at least one lead. A base substrate may also have an opening formed therethrough, the opening defining an interior edge wherein the covercoat extends beyond that interior edge.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: April 13, 2004
    Assignee: 3M Innovative Properties Company
    Inventors: John B. Scheibner, Robert M. Anderton, David L. Buster, Kristine J. Williams
  • Printed circuit substrate with controlled placement covercoat layer
    Patent number: 6423470
    Abstract: A covercoated base substrate, comprising a base substrate and a photoimageable covercoat layer having a lead portion extending beyond at least one, wherein the lead portion has a controlled offset distance from the edge, and a printed circuit made from such base substrate having at least one conductor including a trace and a lead wherein the covercoat has a lead portion covering at least one lead. A base substrate may also have an opening formed therethrough, the opening defining an interior edge wherein the covercoat extends beyond that interior edge.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: July 23, 2002
    Assignee: 3M Innovative Properties Company
    Inventors: John B. Scheibner, Robert M. Anderton, David L. Buster, Kristine J. Williams
  • Printed circuit substrate with controlled placement covercoat layer
    Publication number: 20020037473
    Abstract: A covercoated base substrate, comprising a base substrate and a photoimageable covercoat layer having a lead portion extending beyond at least one, wherein the lead portion has a controlled offset distance from the edge, and a printed circuit made from such base substrate having at least one conductor including a trace and a lead wherein the covercoat has a lead portion covering at least one lead. A base substrate may also have an opening formed therethrough, the opening defining an interior edge wherein the covercoat extends beyond that interior edge.
    Type: Application
    Filed: November 28, 2001
    Publication date: March 28, 2002
    Applicant: 3M Innovative Properties Company
    Inventors: John B. Scheibner, Robert M. Anderton, David L. Buster, Kristine J. Williams