Abstract: A method and apparatus for reducing intermodulation distortion is disclosed. In one embodiment, the method comprises the steps of accepting a sampled input signal V(t) wherein the input signal V(t) comprises a plurality of peaks; determining n peaks Vp1,Vp2, . . . Vpn of the sampled input signal V(t) exceeding a clip value Vclip at times t1, t2, . . . tn; and modifying the sampled input signal V(t) by weighting the n peaks Vp1,Vp2, . . . ,Vpn exceeding the clip value Vclip of the sampled input signal V(t) by a function b(t) wherein b(t) is either a hard limiting function or b(t)=f(a1, a2, . . . an;t?tp1,t?tp2, . . . t?tpn), wherein a1,a2, . . . an are weight values corresponding to the n peaks Vp1, Vp2, . . . Vpn, and f(t?tp1,t?tp2, . . . t?tpn) is a smooth shaping function. Intermodulation performance is then selectively improved in selected sub-bands by notch filtering prior to application to the non-linearity.

Abstract: A method and apparatus for reducing intermodulation distortion is disclosed. In one embodiment, the method comprises the steps of accepting a sampled input signal V(t) wherein the input signal V(t) comprises a plurality of peaks; determining n peaks Vp1,Vp2, . . . ,Vpn of the sampled input signal V(t) exceeding a clip value Vclip at times t1,t2, . . . ,tn; and modifying the sampled input signal V(t) by weighting the n peaks Vp1,Vp2, . . . ,Vpn exceeding the clip value Vclip of the sampled input signal V(t) by a function b(t) wherein b(t) is either a hard limiting function or b(t)=ƒ(a1,a2, . . . an;t-tp1,t-tp2, . . . t-tpn), wherein a1,a2, . . . an are weight values corresponding to the n peaks Vp1,Vp2, . . . ,Vpn, and ƒ(t-tp1,t-tp2, . . . t-tpn) is a smooth shaping function. Intermodulation performance is then selectively improved in selected sub-bands by notch filtering prior to application to the non-linearity.

Abstract: The digital signal is provided to the digital-to-analog upconverter (40) such as through digital signal processing circuitry (70). A sample rate signal and a divided sample rate signal are provided by divider chain (96) using the clock input (44). The divided sample rate signal is used to drive the decode circuit (88). The digital outputs of the decoder circuit (88) is combined with the sample rate signal in a mixer (52) which in turn generates a digitally upconverted signal which drives a plurality of switches combined together to form the analog output (46).

Abstract: A limiter for a solid state power amplifier (SSPA) protects the amplifier against large peak, short duration noise signals while controlling drive level related phase shifts. The limiter limits noise signals to a safe input level for the power output section of the SSPA. It also uses a pair of resistor networks at its input and output to dampen reflected energy and thus control drive level related phase shifts.

Abstract: A predistortion linearizer (10) and method for distorting an AC input signal (42) to a power amplifier (24) provide a distortion to the input signal which is complementary to a distortion, in terms of gain and phase, introduced by the power amplifier as a function of signal amplitude, thereby to linearize the power amplifier. The linearizer includes a switching circuit (26, Z.sub.1 28, Z.sub.2) having an input terminal (16) and an output terminal (20) and a pair of antiparallel diodes (26, 28) connected between the input terminal and the output terminal of the switching circuit. The linearizer has also an impedance circuit (Z.sub.3) comprising solely passive electrical elements connected between the input terminal and the output terminal of the switching circuit, wherein elements of the impedance circuit have values selected to introduce the complementary distortion to the input signal as a function of amplitude of the input signal to linearize the power amplifier.

Abstract: RF power is sampled and measured at the input and output of a solid state power amplifier using directional couplers and matched square law detectors. Outputs from the detectors are applied to differential inputs of a DC operational amplifier. Outputs from the detectors are compared and filtered in the operational amplifier and the resulting difference signal is applied to a control input on a switching type power supply. The power supply converts a DC input voltage to the various positive and negative voltages required to operate the RF devices in the solid state power amplifier. When the control loop is closed, the supply voltage varies to maintain a constant operating point resulting in constant gain, efficiency, and linearity for the overall solid state power amplifier despite variations in signal levels and signal composition. In another embodiment, the solid state power amplifier has a series of single-ended low power amplifiers terminating in an output high power module.