Patents by Inventor David L. Ganapol

David L. Ganapol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5537031
    Abstract: Test jig apparatus for testing an integrated circuit chip that suppresses build-up and subsequent discharge of electrical charge on the test jig apparatus or on the chip. The test jig apparatus includes a base of selected material having a top surface of the same general shape and dimensions as the chip to be tested. Preferably, the entire top surface of the base is electrically grounded. The base has two or more side surfaces with side surface planes that are approximately perpendicular to a plane defining the top surface of the base. Each side surface accepts a side plate, made of a selected material such as ULTIM, that can be attached to or removed from the base. The side plate material resists electrical charge buildup and subsequent discharge so that the chip being tested is not subjected to electrical discharge from this source. In another embodiment, the side plates are replaced by plates mounted on the top surface of the base.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: July 16, 1996
    Assignee: VLSI Technology, Inc.
    Inventors: David L. Ganapol, Arno G. Marcuse
  • Patent number: 5124644
    Abstract: In a system for positioning a semiconductor chip package with respect to a testing surface, the distance between the package or the leads thereof and the testing surface is monitored while the package is pushed towards the testing surface. When the distance monitored falls below a certain value, the package is pushed further by a set distance. In this manner, good contact between the leads of the package and the contacts of the testing surface is achieved without destroying the coplanarity of the leads.
    Type: Grant
    Filed: December 19, 1990
    Date of Patent: June 23, 1992
    Assignee: VLSI Technology, Inc.
    Inventor: David L. Ganapol
  • Patent number: 5110628
    Abstract: A method and apparatus for marking or erasing a marking on a semiconductor chip package having leads. The apparatus comprises a circular disk has many pockets on one surface near its circumference suitable for holding semiconductor chips. Each pocket has a pedestal rising from the bottom of the pocket and suitable for supporting the bottom portion of a semiconductor chip package. The edges of the pocket and the pedestal define between them space suitable for housing the leads of the package. The pedestal has a hole therein which can be evacuated so that the package is held to the pedestal by atmospheric pressure so that the top surface of the package may be marked or in marking thereon can be erased. Thus the package is held to the pedestal by sufficient force for the marking or erasing process. The leads of the package are therefore not bent or otherwise disturbed. Rotation of the disk allows the packages to be sequentially marked or erased.
    Type: Grant
    Filed: March 15, 1990
    Date of Patent: May 5, 1992
    Assignee: VLSI Technology, Inc.
    Inventors: David L. Ganapol, Gary L. Small