Patents by Inventor David L. Harame

David L. Harame has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190341455
    Abstract: A method includes forming a base layer on a top surface of a substrate. A dielectric layer is formed on exposed surfaces of the base layer. A hardmask layer is formed on the base layer and the dielectric layer. A pattern is formed from the hardmask with a first opening and a second opening. Portions of a dielectric layer are removed from the top surface of the base layer at positions consistent with the pattern of the first opening and the second opening to form exposed surfaces defined as a first window and a second window in the dielectric layer. Deposits of a dopant-containing layer are limited on the exposed surfaces of: a first portion on the top surface of the base layer inside of the first window, and a second portion on the top surface of the base layer inside of the second window.
    Type: Application
    Filed: July 19, 2019
    Publication date: November 7, 2019
    Inventors: Renata Camillo-Castillo, David L. Harame, Qizhi Liu
  • Publication number: 20190341454
    Abstract: A device structure for a bipolar junction transistor includes a base layer made of a semiconductor material. An emitter is disposed on a first portion of the base layer. A dopant-containing layer is disposed on a second portion of the base layer. A hardmask is disposed on the base layer. The hardmask includes a window aligned with the second portion of the base layer. Deposits of the dopant-containing layer are limited to exposed surfaces of: the first portion that is disposed on a top surface of the base layer inside of the window.
    Type: Application
    Filed: July 19, 2019
    Publication date: November 7, 2019
    Inventors: Renata Camillo-Castillo, David L. Harame, Qizhi Liu
  • Patent number: 10431654
    Abstract: Device structure and fabrication methods for a bipolar junction transistor. A base layer is formed and an emitter is formed on a first portion of the base layer. A dopant-containing layer is deposited on a second portion of the base layer. Dopant is transferred from the dopant-containing layer into the second portion of the base layer to define an extrinsic base of the device structure.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: October 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, David L. Harame, Qizhi Liu
  • Patent number: 10014397
    Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 3, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Qizhi Liu, David L. Harame, Renata Camillo-Castillo
  • Publication number: 20180175180
    Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 21, 2018
    Inventors: Vibhor Jain, Qizhi Liu, David L. Harame, Renata Camillo-Castillo
  • Patent number: 9758365
    Abstract: Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam from a silicon layer on an insulator. The method further includes providing a coating of insulator material over the single crystalline beam. The method further includes forming a via through the insulator material exposing a wafer underlying the insulator. The insulator material remains over the single crystalline beam. The method further includes providing a sacrificial material in the via and over the insulator material. The method further includes providing a lid on the sacrificial material. The method further includes venting, through the lid, the sacrificial material and a portion of the wafer under the single crystalline beam to form an upper cavity above the single crystalline beam and a lower cavity in the wafer, below the single crystalline beam.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: September 12, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David L. Harame, Anthony K. Stamper
  • Publication number: 20170098699
    Abstract: Device structure and fabrication methods for a bipolar junction transistor. One or more trench isolation regions are formed in a substrate to define a device region having a first width. A protect layer is formed on a top surface of the one or more trench isolation regions and a top surface of the device region. An opening is formed in the protect layer. The opening is coincides with the top surface of the first device region and has a second width that is less than or equal to the first width of the first device region. A base layer is formed that has a first section on the device region inside the first opening and a second section on the protect layer.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Renata Camillo-Castillo, Qizhi Liu, Vibhor Jain, James W. Adkisson, David L. Harame
  • Patent number: 9608096
    Abstract: Device structure and fabrication methods for a bipolar junction transistor. One or more trench isolation regions are formed in a substrate to define a device region having a first width. A protect layer is formed on a top surface of the one or more trench isolation regions and a top surface of the device region. An opening is formed in the protect layer. The opening is coincides with the top surface of the first device region and has a second width that is less than or equal to the first width of the first device region. A base layer is formed that has a first section on the device region inside the first opening and a second section on the protect layer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: March 28, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Renata Camillo-Castillo, Qizhi Liu, Vibhor Jain, James W. Adkisson, David L. Harame
  • Patent number: 9583569
    Abstract: Device structures for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: February 28, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Renata Camillo-Castillo, David L. Harame, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
  • Patent number: 9570564
    Abstract: Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: February 14, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Deborah A. Alperstein, David L. Harame, Alvin J. Joseph, Qizhi Liu, Keith J. Machia, Christa R. Willets
  • Patent number: 9553145
    Abstract: Methods of forming bipolar device structures and bipolar device structures. An opening may be formed in a device layer of a silicon-on-insulator substrate that extends to a buried insulator layer of the silicon-on-insulator substrate. An intrinsic base layer may be grown within the device layer opening by lateral growth on opposite first and second sidewalls of the device layer bordering the opening. A first collector of a first bipolar junction transistor of the device structure may be formed at a first spacing from the first sidewall. A second collector of a second bipolar junction transistor of the device structure may be formed at a second spacing from the second sidewall. An emitter, which is shared by the first bipolar junction transistor and the second bipolar transistor, is formed inside the opening. Portions of the intrinsic base layer may supply respective intrinsic bases for the first and second bipolar junction transistors.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: David L. Harame, Michael L. Kerbaugh, Qizhi Liu
  • Publication number: 20160380055
    Abstract: Device structure and fabrication methods for a bipolar junction transistor. A base layer is formed and an emitter is formed on a first portion of the base layer. A dopant-containing layer is deposited on a second portion of the base layer. Dopant is transferred from the dopant-containing layer into the second portion of the base layer to define an extrinsic base of the device structure.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Renata Camillo-Castillo, David L. Harame, Qizhi Liu
  • Publication number: 20160225917
    Abstract: At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.
    Type: Application
    Filed: April 7, 2016
    Publication date: August 4, 2016
    Inventors: James W. Adkisson, James S. Dunn, Blaine J. Gross, David L. Harame, Qizhi Liu, John J. Pekarik
  • Publication number: 20160190292
    Abstract: The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer.
    Type: Application
    Filed: March 4, 2016
    Publication date: June 30, 2016
    Inventors: James W. Adkisson, David L. Harame, Michael L. Kerbaugh, Qizhi Liu, John J. Pekarik
  • Patent number: 9362229
    Abstract: Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jeffrey P. Gambino, David L. Harame, Baozhen Li, Timothy D. Sullivan, Bjorn K. A. Zetterlund
  • Patent number: 9356097
    Abstract: Embodiments of the present invention include a method for forming a semiconductor emitter and the resulting structure. The invention comprises forming an epitaxial base layer on a semiconductor substrate. A dielectric layer is deposited over the epitaxial base layer. An opening is etched in a portion of the dielectric layer exposing a portion of the epitaxial base layer and a spacer is deposited along the sidewall of the opening. The emitter is grown from the epitaxial base layer to overlap the top surface of the spacer and a portion of the dielectric layer. The single crystal emitter is formed without a mask and without the requirement of subsequent patterning processes.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: May 31, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David L. Harame, Vikas K. Kaushal, Marwan H. Khater, Qizhi Liu
  • Patent number: 9349845
    Abstract: Device structures and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate. The intrinsic base and terminal are respectively comprised of first and second semiconductor materials.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David L. Harame, Qizhi Liu
  • Patent number: 9343589
    Abstract: At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: May 17, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: James W. Adkisson, James S. Dunn, Blaine J. Gross, David L. Harame, Qizhi Liu, John J. Pekarik
  • Publication number: 20160104770
    Abstract: Device structures for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.
    Type: Application
    Filed: December 14, 2015
    Publication date: April 14, 2016
    Inventors: Renata Camillo-Castillo, David L. Harame, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
  • Patent number: 9312370
    Abstract: The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: April 12, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: James W. Adkisson, David L. Harame, Michael L. Kerbaugh, Qizhi Liu, John J. Pekarik