Abstract: Performance monitor apparatus is adapted to monitor various computer program events such as the length of time required to execute a particular program, the number of times a particular program or instruction sequence is executed during some predetermined period, etc. The apparatus includes a buffer for receiving an instruction data word from a data processor and for temporarily storing the data word, a register having a plurality of bistable elements each of which is adapted to produce either a first or second output signal in response to receipt of a first or second operation signal respectively and receipt of a select signal, a select logic circuit for applying a select signal to a particular bistable element identified by certain bits of the instruction data word stored in the buffer, and an operation logic circuit for supplying to the bistable elements either a first or second operation signal as determined by certain other bits of the instruction data word stored in the buffer.