Patents by Inventor David L. Hill
David L. Hill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160332645Abstract: A method and system for verifying trackside conditions in safety critical railroad applications by reporting the status of trackside signals and switches to a remote train control system. The system comprises at least one sensor for providing trackside conditions electrically connected to a circuit for providing trackside conditions to a railroad, said sensor being powered by voltage applied to the circuit such that the sensor is energized only when said electrical component is engaged. The system and method further comprises a method and system which is failsafe and which enables the control system to independently verify signals from each sensor.Type: ApplicationFiled: July 29, 2016Publication date: November 17, 2016Inventors: FRANCOIS PRETORIUS, DAVID L. HILL, CHARLES A. WISNIEWSKI, LAWRENCE DELOSS LOWE, III
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Patent number: 9457821Abstract: A method and system for verifying trackside conditions in safety critical railroad applications by reporting the status of trackside signals and switches to a remote train control system. The system comprises at least one sensor for providing trackside conditions electrically connected to a circuit for providing trackside conditions to a railroad, said sensor being powered by voltage applied to the circuit such that the sensor is energized only when said electrical component is engaged. The system and method further comprises a method and system which is failsafe and which enables the control system to independently verify signals from each sensor.Type: GrantFiled: March 20, 2015Date of Patent: October 4, 2016Assignee: WESTINGHOUSE AIR BRAKE TECHNOLOGIES CORPORATIONInventors: Francois Pretorius, David L. Hill, Charles A. Wisniewski, Lawrence Deloss Lowe, III
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Publication number: 20150191185Abstract: A method and system for verifying trackside conditions in safety critical railroad applications by reporting the status of trackside signals and switches to a remote train control system. The system comprises at least one sensor for providing trackside conditions electrically connected to a circuit for providing trackside conditions to a railroad, said sensor being powered by voltage applied to the circuit such that the sensor is energized only when said electrical component is engaged. The system and method further comprises a method and system which is failsafe and which enables the control system to independently verify signals from each sensor.Type: ApplicationFiled: March 20, 2015Publication date: July 9, 2015Inventors: FRANCOIS PRETORIUS, DAVID L. HILL, CHARLES A. WISNIEWSKI, LAWRENCE DELOSS LOWE, III
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Patent number: 8989926Abstract: A method and system for verifying trackside conditions in safety critical railroad applications by reporting the status of trackside signals and switches to a remote train control system. The system comprises at least one sensor for providing trackside conditions electrically connected to a circuit for providing trackside conditions to a railroad, said sensor being powered by voltage applied to the circuit such that the sensor is energized only when said electrical component is engaged. The system and method further comprises a method and system which is failsafe and which enables the control system to independently verify signals from each sensor.Type: GrantFiled: November 18, 2009Date of Patent: March 24, 2015Assignee: Convergent Communications, Inc.Inventors: Francois Pretorius, David L. Hill, Lawrence Deloss Lowe, III, Charles A. Wisniewski
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Patent number: 8205111Abstract: In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.Type: GrantFiled: January 2, 2009Date of Patent: June 19, 2012Assignee: Intel CorporationInventors: David L. Hill, Robert J. Greiner, Tim Frodsham, Derek Bachand, Anant Deval, Mark Waggoner
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Publication number: 20110118913Abstract: The present invention discloses an improved method and system for verifying trackside conditions in safety critical railroad applications by reporting the status of trackside signals and switches to a remote train control system to confirm visual signals and control train movement. The system for verifying whether a trackside signaling electrical component is energized comprises a sensor for providing trackside conditions to a remote train control system electrically connected to a circuit for providing trackside conditions to a railroad interlocking adjacent to a trackside signaling electrical component, said sensor powered by voltage applied to said circuit such that said sensor is energized only when said electrical component is engaged.Type: ApplicationFiled: November 18, 2009Publication date: May 19, 2011Applicant: CONVERGENT COMMUNICATIONS, INC.Inventors: Francois Pretorius, David L. Hill, Lawrence Deloss Lowe, III, Charles A. Wisniewski
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Patent number: 7783809Abstract: Architectures and techniques that allow legacy pin functionality to be replaced with a “virtual wire” that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.Type: GrantFiled: June 30, 2005Date of Patent: August 24, 2010Assignee: Intel CorporationInventors: Keshavan K. Tiruvallur, David I. Poisner, Herbert H. J. Hum, Frank Binns, David L. Hill, Robert J. Greiner, Raymond S. Tetrick
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Publication number: 20100174936Abstract: In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.Type: ApplicationFiled: January 2, 2009Publication date: July 8, 2010Inventors: David L. Hill, Robert J. Greiner, Tim Frodsham, Derek Bachand, Anant Deval, Mark Waggoner
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Patent number: 7487305Abstract: A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.Type: GrantFiled: November 7, 2006Date of Patent: February 3, 2009Assignee: Intel CorporationInventors: David L. Hill, Derek T. Bachand
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Patent number: 7363474Abstract: Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes resumption of the first thread in response to an access to the specified monitor address.Type: GrantFiled: December 31, 2001Date of Patent: April 22, 2008Assignee: Intel CorporationInventors: Dion Rodgers, Deborah T. Marr, David L. Hill, Shiv Kaushik, James B. Crossland, David A. Koufaty
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Patent number: 7143242Abstract: A multi-mode transaction queue may operate according to a default priority scheme. When a congestion event is detected, the transaction queue may engage a second priority scheme.Type: GrantFiled: September 23, 2003Date of Patent: November 28, 2006Assignee: Intel CorporationInventors: David L. Hill, Derek T. Bachand, Chinna B. Prudvi, Deborah T. Marr
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Patent number: 7133981Abstract: A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.Type: GrantFiled: May 11, 2004Date of Patent: November 7, 2006Assignee: Intel CorporationInventors: David L Hill, Derek T. Bachand
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Patent number: 7127561Abstract: Coherency techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes a cache, execution logic to execute an instruction having an operand indicating a monitor address and a bus controller. In one embodiment, the bus controller is to assert a preventative signal in response to receiving a memory access attempting to gain sufficient ownership of a cache line associated with said monitor address to allow modification of said cache line without generation of another transaction indicative of the modification. In another embodiment, the bus controller is to generate a bus cycle in response to the instruction to eliminate any ownership of the cache line by another processor that would allow a modification of the cache line without generation of another memory access indicative of the modification.Type: GrantFiled: December 31, 2001Date of Patent: October 24, 2006Assignee: Intel CorporationInventors: David L. Hill, Deborah T. Marr, Dion Rodgers, Shiv Kaushik, James B. Crossland, David A. Koufaty
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Patent number: 6907487Abstract: A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to drive data elements at four times the clock frequency. The address bus interface drives a substantially centered address strobe transition for each address element, and the data bus interface drives a substantially centered data strobe transition for each data element.Type: GrantFiled: February 14, 2001Date of Patent: June 14, 2005Assignee: Intel CorporationInventors: Gurbir Singh, Robert J. Greiner, Stephen S. Pawlowski, David L. Hill, Donald D. Parker
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Patent number: 6880031Abstract: A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a set of snoop status interfaces, an address strobe signal interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic capable of sensing or asserting one or more of a set of snoop status signals for transaction N on the snoop status interfaces during a snoop phase to start in a bus cycle upon the later of three or more bus clock cycles of the bus clock signal after a beginning of a bus cycle of an the assertion of an address strobe signal for transaction N or two or more bus clock cycles of the bus clock signal after a beginning of a bus cycle in which a most recent snoop phase begins.Type: GrantFiled: February 14, 2001Date of Patent: April 12, 2005Assignee: Intel CorporationInventors: Gurbir Singh, Robert J. Greiner, Stephen S. Pawlowski, David L. Hill, Donald D. Parker
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Patent number: 6807592Abstract: A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g.Type: GrantFiled: August 10, 2001Date of Patent: October 19, 2004Assignee: Intel CorporationInventors: Gurbir Singh, Robert J. Greiner, Stephen S. Pawlowski, David L. Hill, Donald D. Parker
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Patent number: 6804735Abstract: A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a target ready interface, a set of response interfaces for a set of response signals, and a data bus busy interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic to track a plurality of transactions comprising a transaction N-1 and a transaction N, the bus controller being capable of asserting the target ready signal for transaction N if the bus agent is asserting the data busy signal for the transaction N-1 and deasserts the data busy signal.Type: GrantFiled: February 14, 2001Date of Patent: October 12, 2004Assignee: Intel CorporationInventors: Gurbir Singh, Robert J. Greiner, Stephen S. Pawlowski, David L. Hill, Donald D. Parker
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Patent number: 6782457Abstract: A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.Type: GrantFiled: June 5, 2003Date of Patent: August 24, 2004Assignee: Intel CorporationInventors: David L Hill, Derek T. Bachand
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Patent number: 6742085Abstract: A prefetching control system provided for a processor. The prefetching queue may include an arbiter, a cache queue and a prefetch queue. The arbiter issues requests including read requests. Responsive to a read request, the cache queue issues a control signal. The prefetch queue receives the control signal and an address associated with the read request. When the received address is a member of a pattern of read requests from sequential memory locations, the prefetch queue issues a prefetch request to the arbiter.Type: GrantFiled: April 1, 2003Date of Patent: May 25, 2004Assignee: Intel CorporationInventors: David L. Hill, Chlnna B. Prudvi
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Patent number: 6732242Abstract: A transaction management system is described for scheduling requests on an external bus. The system includes a number of queue registers to store requests and a controller coupled to queue registers to schedule external bus transactions for an agent that processes read requests, prefetch requests and write requests. The controller posts at least one write request to an external bus every defined number of transactions if at least one non-posted write request is stored in the queue registers.Type: GrantFiled: March 28, 2002Date of Patent: May 4, 2004Assignee: Intel CorporationInventors: David L. Hill, Paul D. Breuder, Robert J. Greiner, Derek T. Bachand