Abstract: The invention provides a method and system for operating a pipelined microprocessor more quickly, by detecting instructions that load from identical memory locations as were recently stored to, without having to actually compute the referenced external memory addresses. The microprocessor examines the symbolic structure of instructions as they are encountered, so as to be able to detect identical memory locations by examination of their symbolic structure. For example, in a preferred embodiment, instructions that store to and load from an identical offset from an identical register are determined to be referencing the identical memory location, without having to actually compute the complete physical target address.

Abstract: A method and mechanism for managing operating system instances in a computing system. A computing system is configured to enable users to model and manage operating system instances. One or more defined operating system instances may be created and stored for future use. Each of the defined operating system instances may include a description of required resources. In addition, the definition of desired and/or optimal resources may be specified. In response to an attempt to realize an operating system instance, a determination is made as to whether resources allocated for the operating system instance are adequate. If the allocated resources are inadequate, further resources may be allocated. In addition, a determination may be made as to whether a standby mode is indicated for the operating system instance. If a standby mode is indicated, the operating system instance may be realized but not booted.

Abstract: A method for expressing the algorithms for the manipulation of hardware includes providing program instructions that describe a sequence of one or more transactions for manipulating hardware components of a system. The program instructions may call one or more code segments that include specific information associated with particular hardware components of the system. In addition, the program instructions are independent of the specific information. The method may also include translating the program instructions into an executable form and executing the executable form of the program instructions to manipulate the hardware components of the system from one consistent state to a next consistent state.

Abstract: In one embodiment, an apparatus comprises a plurality of core logic blocks, a plurality of first event blocks, and a second event block. Each of the plurality of core logic blocks is configured to generate one or more indications of one or more events. Each first event block of the plurality of first event blocks is coupled to a respective core logic block of the plurality of core logic blocks to receive the one or more indications from the respective core logic block. Each first event block comprises at least one register configured to record which events have been indicated by the respective core logic block. Coupled to the plurality of first event blocks, the second event block is configured to initiate one or more actions responsive to one or more events detected in one or more of the plurality of first event blocks.

Abstract: A method of utilizing timestamps for the global ordering of event information, particularly hardware error reporting, is disclosed. Locally generated time stamps are associated with hardware errors or other events. The timestamps form the basis for the global ordering of event information. The timestamps are normalized, either through a pre-synchronization process with a common time, or through the use of offsets maintained either locally near system chips or by the system processor. Once normalized, the timestamps can be compared to determine a first occurring event among multiple reported events.

Abstract: The invention provides a method and system for performing instructions in a microprocessor having a set of registers, in which instructions which operate on portions of a register are recognized, and “stitching” instructions are inserted into the instruction stream to couple the instructions operating on the portions of the register. The “stitching” parcels are serialized along with other instruction parcels, so that instructions which read from or write to portions of a register can proceed independently and out of their original order, while maintaining the results of that out-or-order operation to be the same as if all instructions were performed in the original order. In a preferred embodiment, the choice of stitching parcels is optimized to the Intel x86 architecture and instruction set.

Abstract: A system for processing a floating point instruction includes a stack, virtual registers, a stack pointer pointing to one of the virtual registers as top of stack, physical registers, and a reference table mapping the virtual registers to the physical registers, entries of the reference table pointing to physical register locations. An instruction unit generates a plurality of instructions, and a decode unit having a plurality of decoders receives the plurality of instructions from the instruction unit, respectively. The decode unit decodes the plurality of instructions and determines whether any one of the instructions contains a floating point instruction including a floating point exchange instruction. A logic unit is coupled to the reference table and includes a plurality of logic devices coupled to the plurality of decoders in the decode unit, respectively.

Abstract: Apparatus for detecting and executing trapping program instructions in a superscalar processor operating on a plurality of pipelined instructions includes a fetch stage for fetching consecutive instructions from an instruction cache or from main memory, an instruction FIFO memory for storing fetched instructions from the fetch stage, and an instruction decode stage for removing instructions from the FIFO memory in accordance with relative ages of instructions stored in the FIFO memory. The decode stage examines instructions removed from the FIFO memory for trapping conditions, and flushes all younger instructions from the FIFO memory in response to identification of a trap in an instruction. The decode stage distinguishes between hardware traps and software traps. A software trapping instruction is forwarded to an execute stage for execution. The decode stage immediately causes the fetch address to be changed to the appropriate trap handler address.

Abstract: A branch prediction technique which increases the likelihood of correctly predicting the direction of a conditional branch instruction is presented. The technique is based on the observation that many branches have run lengths that are constant or slowly-varying. I.e., several consecutive runs of 1's are of the same length. The technique uses the history stored for each branch, which history is enhanced by two small counters, an up counter and a down counter. These counters operate in conjunction with a state machine branch predictor of the prior art for very accurate predictions.

Abstract: A data processing system includes an instruction unit generating a program instruction. A parse unit coupled to the instruction unit receives the program instruction. The parse unit determines whether the instruction contains both load and store operations and generates first and second parcels for the instruction containing both load and store operations. A decode unit coupled to the parse unit receives the first and second parcels. The decode unit attaches an identification number to the first and second parcels, the identification number of the second parcel being determinable from the identification number of the first parcel. An issue unit coupled to the decode unit receives the first and second parcels. The issue unit issues the parcels to an instruction shelf, a load shelf, and a store shelf for instruction execution.

Abstract: Apparatus for detecting and executing trapping program instructions in a superscalar processor operating on a plurality of pipelined instructions includes a fetch stage for fetching consecutive instructions from an instruction cache or from main memory, an instruction FIFO memory for storing fetched instructions from the fetch stage, and an instruction decode stage for removing instructions from the FIFO memory in accordance with relative ages of instructions stored in the FIFO memory. The decode stage examines instructions removed from the FIFO memory for trapping conditions, and flushes all younger instructions from the FIFO memory in response to identification of a trap in an instruction. The decode stage distinguishes between hardware traps and software traps. A software trapping instruction is forwarded to an execute stage for execution. The decode stage immediately causes the fetch address to be changed to the appropriate trap handler address.

Abstract: A method of transmitting isochronous and nonisochronous data in a computer network in which multiple stations have respective input and output ports that are serially coupled together to form a loop includes the steps of: transmitting nonisochronous data from one station of the network and passing it through the remaining stations; periodically inserting into the nonisochronous data a lead control character followed by a trail control character and circulating the control characters twice around the network; increasing, in any station of the network that has isochronous data to send, the distance between the lead and trail control characters and sending isochronous data immediately before the trail control character as it passes through the station; subsequently decreasing the distance between the lead and trail control characters in each station of the network that performs the sending step by removing, from immediately behind the first lead control character to enter the station after the sending step begin

Abstract: A method of transmitting isochronous and nonisochronous data through a computer network in which a plurality of stations have respective input and output ports that are serially coupled together to form a loop includes the steps of: transmitting data characters of a nonisochronous frame from a first station in the loop; passing the data characters from the first station through a second station in the loop but with a pair of control characters inserted between any two data characters indicating the beginning and end of an isochronous frame within the nonisochronous frame; passing the data characters and control characters from the second station through a third station on the loop but with another internally generated isochronous data character inserted between the control characters; temporarily stopping the transmitting step in the first station in response to the receipt of at least one of the control characters to pass the isochronous frame through the first station; and proceeding in the first station wi

Abstract: Disclosed is a digital computer that includes a memory means in which each of the instructions that the computer executes is represented by first, second, and third sets of microcommands. For any one particular instruction, the first set of microcommands is executed before the second set and the second set is executed before the third set. But the computer also includes a control means which directs the execution of the microcommand sets such that between the execution of the first and second microcommand sets for one instruction there is executed the third microcommand set for a prior instruction, and between the execution of the second and third microcommand sets for that same one instruction there is executed the first microcommand set for a subsequent instruction.