Abstract: A number of adder structures (also referred to herein as "tiles" and "Quickadders.TM.") are provided which may be constructed with positively and/or negatively weighted and signed inputs and outputs and which may be placed so as to span one or more bitslices of a multiplier array. In a second aspect of the present invention, groups of replicable circuitry columns are provided for forming multiplier arrays for multiplying binary numbers X and Y to obtain a binary product Z. These groups of columns of circuitry include left column groups to handle X-inputs to the array, internal column groups, and right column groups to handle outputs to a CLA adder/subtractor (or equivalent) for processing the MSBs of the product. The LSBs of the product are produced directly by the array. The groups may be thought of as replacing 2, 3 or 4 conventional columns of full-adder circuitry of a basic array such as that shown in FIGS. 1 and 2.

Abstract: A circuit design tool which includes (1) separating structural and functional aspects of components, so as to specify the desired functional behaviour of the component, leaving the actual gate-level design of the component to the design tool; (2) translating a model of the desired logical behaviour of a circuit into a regularized set of functional components to achieve that desired behaviour; (3) verifying structural equivalence between pairs of components; (4) a method for bit-reversing the signal flow in a component; (5) a method for performing arithmetic operations backwards from a natural order; (6) an architecture for a multiplier which is faster and more compact than known multipliers; and (7) a method of translating a logic equation into a netlist of connected logic gates.

Abstract: A circuit design tool which includes an architecture for a multiplier which is faster and more compact than known multipliers through the use of Wallace trees, the elimination of Dadda nodes along the critical paths, the placement of half-adders at an initial pat of the Wallace tree, the replacement of low-order terminating adders with ripple-carry adders, and the replacement of high-order terminating adders with carry-select adders.