Patents by Inventor David L. Keating
David L. Keating has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240068135Abstract: Interlacing equipment may be used to form fabric and to create a gap in the fabric. The fabric may include one or more conductive strands. An insertion tool may be used to align an electrical component with the conductive strands during interlacing operations. A soldering tool may be used to remove insulation from the conductive strands to expose conductive segments on the conductive strands. The soldering tool may be used to solder the conductive segments to the electrical component. The solder connections may be located in grooves in the electrical component. An encapsulation tool may dispense encapsulation material in the grooves to encapsulate the solder connections. After the electrical component is electrically connected to the conductive strands, the insertion tool may position and release the electrical component in the gap. A component retention tool may temporarily be used to retain the electrical component in the gap as interlacing operations continue.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Inventors: Kyle L. Chatham, Kathryn P. Crews, Didio V. Gomes, Benjamin J. Grena, Storrs T. Hoen, Steven J. Keating, David M. Kindlon, Daniel A. Podhajny, Andrew L. Rosenberg, Daniel D. Sunshine, Lia M. Uesato, Joseph B. Walker, Felix Binder, Bertram Wendisch, Martin Latta, Ulrich Schläpfer, Franck Robin, Michael Baumann, Helen Wächter Fischer
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Patent number: 11913143Abstract: Interlacing equipment may be used to form fabric and to create a gap in the fabric. The fabric may include one or more conductive strands. An insertion tool may be used to align an electrical component with the conductive strands during interlacing operations. A soldering tool may be used to remove insulation from the conductive strands to expose conductive segments on the conductive strands. The soldering tool may be used to solder the conductive segments to the electrical component. The solder connections may be located in grooves in the electrical component. An encapsulation tool may dispense encapsulation material in the grooves to encapsulate the solder connections. After the electrical component is electrically connected to the conductive strands, the insertion tool may position and release the electrical component in the gap. A component retention tool may temporarily be used to retain the electrical component in the gap as interlacing operations continue.Type: GrantFiled: March 4, 2020Date of Patent: February 27, 2024Assignee: Apple Inc.Inventors: Kyle L Chatham, Kathryn P. Crews, Didio V. Gomes, Benjamin J. Grena, Storrs T. Hoen, Steven J. Keating, David M. Kindlon, Daniel A. Podhajny, Andrew L. Rosenberg, Daniel D. Sunshine, Lia M. Uesato, Joseph B. Walker, Felix Binder, Bertram Wendisch, Martin Latta, Ulrich Schläpfer, Franck Robin, Michael Baumann, Helen Wächter Fischer
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Patent number: 6122756Abstract: A high availability computer system and methodology including a backplane, having at least one backplane communication bus and a diagnostic bus, a plurality of motherboards, each interfacing to the diagnostic bus. Each motherboard also includes a memory system including main memory distributed among the plurality of motherboards and a memory controller module for accessing said main memory interfacing to said motherboard communication bus. Each motherboard also includes at least one daughterboard, detachably connected to thereto. The motherboard further includes a backplane diagnostic bus interface mechanism interfacing each of the motherboards to the backplane diagnostic bus; a microcontroller for processing information and providing outputs and a test bus controller mechanism including registers therein.Type: GrantFiled: February 10, 1998Date of Patent: September 19, 2000Assignee: Data General CorporationInventors: William F. Baxter, Robert G. Gelinas, James M. Guyer, Dan R. Huck, Michael F. Hunt, David L. Keating, Jeff S. Kimmell, Phil J. Roux, Liz M. Truebenbach, Rob P. Valentine, Pat J. Weiler, Joseph Cox, Barry E. Gillott, Andrea Heyda, Rob J. Pike, Tom V. Radogna, Art A. Sherman, Micheal Sporer, Doug J. Tucker, Simon N. Yeung
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Patent number: 6026461Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency.Type: GrantFiled: December 9, 1998Date of Patent: February 15, 2000Assignee: Data General CorporationInventors: William F. Baxter, Robert G. Gelinas, James M. Guyer, Dan R. Huck, Michael F. Hunt, David L. Keating, Jeff S. Kimmell, Phil J. Roux, Liz M. Truebenbach, Rob P. Valentine, Pat J. Weiler, Joseph Cox, Barry E. Gillott, Andrea Heyda, Rob J. Pike, Tom V. Radogna, Art A. Sherman, Michael Sporer, Doug J. Tucker, Simon N. Yeung
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Patent number: 5887146Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency.Type: GrantFiled: August 12, 1996Date of Patent: March 23, 1999Assignee: Data General CorporationInventors: William F. Baxter, Robert G. Gelinas, James M. Guyer, Dan R. Huck, Michael F. Hunt, David L. Keating, Jeff S. Kimmell, Phil J. Roux, Liz M. Truebenbach, Rob P. Valentine, Pat J. Weiler, Joseph Cox, Barry E. Gillott, Andrea Heyda, Rob J. Pike, Tom V. Radogna, Art A. Sherman, Michael Sporer, Doug J. Tucker, Simon N. Yeung
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Patent number: 5155818Abstract: A method and system for handling a branch instruction which requires branching from a current instruction of a first instruction sequence to the first instruction of a second instruction sequence. The branch instruction is fetched and the next instruction of the first sequence is fetched while the branch instruction is displacement formatted. The first instruction of the second sequence is fetched while such next instruction is displacement formatted and the branch instruction is executed. The second instruction of the second sequence is fetched while the first instruction is displacement formatted, but the next instruction of the first sequence is not executed so that an execution wait occurs. The third instruction of the second sequence is then fetched while the second instruction is displacement formatted and the first instruction is executed.Type: GrantFiled: September 28, 1988Date of Patent: October 13, 1992Assignee: Data General CorporationInventors: James B. Stein, David L. Keating, Richard W. Reeves
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Patent number: 4597041Abstract: A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a malfunction nibble shifter, and a high speed look-aside memory control.Type: GrantFiled: November 15, 1982Date of Patent: June 24, 1986Assignee: Data General Corp.Inventors: James M. Guyer, David I. Epstein, David L. Keating, Walker Anderson, James E. Veres, Harold R. Kimmens
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Patent number: 4591972Abstract: A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a multifunction nibble shifter, and a high speed look-aside memory control. Adaptive microcode control means 272 are disclosed in which microinstruction sequencing is a function 273 of the current microinstruction and current machine state.Type: GrantFiled: November 15, 1982Date of Patent: May 27, 1986Assignee: Data General Corp.Inventors: James M. Guyer, David I. Epstein, David L. Keating
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Patent number: 4569018Abstract: A data processing uses instructions which may refer to operands in main memory by either physical or logical addresses. The central processor has an internal memory organized as two portions. The first portion provides a scratchpad memory function for the central processor and the second portion is responsive to logical addresses to provide corresponding physical addresses.Type: GrantFiled: November 15, 1982Date of Patent: February 4, 1986Assignee: Data General Corp.Inventors: Mark D. Hummel, James M. Guyer, David I. Epstein, David L. Keating, Steven J. Wallach
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Patent number: 4409655Abstract: A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses. The system uses hierarchical memory storage using in a particular embodiment eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The segment locations are designated by successive segment numbers having a descending order of protection with reference to data accesses thereto. A current address for data access includes a segment identification and a comparison is made with the segment identification of a preceding address to determine whether access can be made by the current address.Type: GrantFiled: April 25, 1980Date of Patent: October 11, 1983Assignee: Data General CorporationInventors: Steven Wallach, Kenneth D. Holberger, David L. Keating, Steven M. Staudaher