Patents by Inventor David L. Kreitzer
David L. Kreitzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10656947Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.Type: GrantFiled: March 14, 2018Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Maxim Loktyukhin, Eric W. Mahurin, Bret L. Toll, Martin G. Dixon, Sean P. Mirkes, David L. Kreitzer, Elmoustapha Ould-Ahmed-Vall, Vinodh Gopal
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Patent number: 10579379Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.Type: GrantFiled: December 12, 2014Date of Patent: March 3, 2020Assignee: INTEL CORPORATIONInventors: Maxim Loktyukhin, Eric W Mahurin, Bret L Toll, Martin G Dixon, Sean P Mirkes, David L Kreitzer, Elmoustapha Ould-Ahmed-Vall, Vinodh Gopal
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Patent number: 10579380Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.Type: GrantFiled: December 12, 2014Date of Patent: March 3, 2020Assignee: INTEL CORPORATIONInventors: Maxim Loktyukhin, Eric W Mahurin, Bret L Toll, Martin G Dixon, Sean P Mirkes, David L Kreitzer, Elmoustapha Ould-Ahmed-Vall, Vinodh Gopal
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Patent number: 10372455Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.Type: GrantFiled: December 12, 2014Date of Patent: August 6, 2019Assignee: Intel CorporationInventors: Maxim Loktyukhin, Eric W Mahurin, Bret L Toll, Martin G Dixon, Sean P Mirkes, David L Kreitzer, Elmoustapha Ould-Ahmed-Vall, Vinodh Gopal
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Patent number: 10268454Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector load operations. An example apparatus includes a node grouper to associate a vector operation with a node group, a candidate verifier to perform a dependencies test on a subset of the node group, and identify a subset of the node group as a candidate when the subset satisfies the dependencies test, and a code optimizer to determine replacement code based on a characteristic of the candidate in the node group and compare an estimated cost associated with executing the replacement code to a threshold. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold.Type: GrantFiled: September 25, 2017Date of Patent: April 23, 2019Assignee: Intel CorporationInventors: Farhana Aleen Schuchman, David L. Kreitzer, Rakesh Krishnaiyer, Vyacheslav Pavlovich Zakharin, Sergey Preis, Leonardo Jose Borges, Philippe Thierry
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Publication number: 20180203698Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.Type: ApplicationFiled: March 14, 2018Publication date: July 19, 2018Applicant: Intel CorporationInventors: Maxim Loktyukhin, Eric W. Mahurin, Bret L. Toll, Martin G. Dixon, Sean P. Mirkes, David L. Kreitzer, Elmoustapha Ould-Ahmed-Vall, Vinodh Gopal
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Publication number: 20180011693Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector load operations. An example apparatus includes a node grouper to associate a vector operation with a node group, a candidate verifier to perform a dependencies test on a subset of the node group, and identify a subset of the node group as a candidate when the subset satisfies the dependencies test, and a code optimizer to determine replacement code based on a characteristic of the candidate in the node group and compare an estimated cost associated with executing the replacement code to a threshold. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold.Type: ApplicationFiled: September 25, 2017Publication date: January 11, 2018Inventors: Farhana Aleen Schuchman, David L. Kreitzer, Rakesh Krishnaiyer, Vyacheslav Pavlovich Zakharin, Sergey Preis, Leonardo Jose Borges, Philippe Thierry
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Patent number: 9785413Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector loads. An example apparatus includes a node group to associate a vector operation with a node group based on a load type of the vector operation. The example apparatus also includes a candidate identifier to identify a candidate in the node group, the candidate to include a subset of vector operations of the node group. The example apparatus also includes a code optimizer to determine replacement code based on a characteristic of the candidate, and to compare an estimated cost associated with executing the replacement code to a threshold cost relative to a cost of executing the candidate. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold cost.Type: GrantFiled: June 16, 2015Date of Patent: October 10, 2017Assignee: INTEL CORPORATIONInventors: Farhana Aleen Schuchman, David L. Kreitzer, Rakesh Krishnaiyer, Vyacheslav Pavlovich Zakharin, Sergey Preis, Leonardo Jose Borges, Philippe Thierry
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Publication number: 20160259628Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector loads. An example apparatus includes a node group to associate a vector operation with a node group based on a load type of the vector operation. The example apparatus also includes a candidate identifier to identify a candidate in the node group, the candidate to include a subset of vector operations of the node group. The example apparatus also includes a code optimizer to determine replacement code based on a characteristic of the candidate, and to compare an estimated cost associated with executing the replacement code to a threshold cost relative to a cost of executing the candidate. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold cost.Type: ApplicationFiled: June 16, 2015Publication date: September 8, 2016Inventors: Farhana Aleen Schuchman, David L. Kreitzer, Rakesh Krishnaiyer, Vyacheslav Pavlovich Zakharin, Sergey Preis, Leonardo Jose Borges, Philippe Thierry
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Publication number: 20150143084Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.Type: ApplicationFiled: December 12, 2014Publication date: May 21, 2015Applicant: INTEL CORPORATIONInventors: Maxim Loktyukhin, Eric W. Mahurin, Bret L. Toll, Martin G. Dixon, Sean P. Mirkes, David L. Kreitzer, ELMOUSTAPHA OULD-AHMED-VALL, Vinodh Gopal
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Publication number: 20150100761Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.Type: ApplicationFiled: December 12, 2014Publication date: April 9, 2015Applicant: INTEL CORPORATIONInventors: Maxim Loktyukhin, Eric W Mahurin, Bret L Toll, Martin G Dixon, Sean P Mirkes, David L Kreitzer, ELMOUSTAPHA OULD-AHMED-VALL, Vinodh Gopal
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Publication number: 20150100760Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.Type: ApplicationFiled: December 12, 2014Publication date: April 9, 2015Applicant: INTEL CORPORATIONInventors: Maxim Loktyukhin, Eric W Mahurin, Bret L Toll, Martin G Dixon, Sean P Mirkes, David L Kreitzer, ELMOUSTAPHA OULD-AHMED-VALL, Vinodh Gopal
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Patent number: 9003170Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.Type: GrantFiled: December 22, 2009Date of Patent: April 7, 2015Assignee: Intel CorporationInventors: Maxim Loktyukhin, Eric W. Mahurin, Bret L. Toll, Martin G. Dixon, Sean P. Mirkes, David L. Kreitzer, El Moustapha Ould-Ahmed-Vall, Vinodh Gopal
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Publication number: 20110153997Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.Type: ApplicationFiled: December 22, 2009Publication date: June 23, 2011Inventors: Maxim Loktyukhin, Eric W. Mahurin, Bret L. Toll, Martin G. Dixon, Sean P. Mirkes, David L. Kreitzer, El Moustapha Ould-Ahmed-Vall, Vinodh Gopal
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Patent number: 6671873Abstract: An automated method for determining problematic binary files. A group of source code files is compiled using two different compiling environments. One of the compiling environments yields a failing set of binary files (i.e., the resultant executable program exhibits problematic behavior). The other compiling environment yields a passing set of binary files (i.e., the resultant executable program does not exhibit problematic behavior). Complementary sets of files, containing some passing files and some failing files, are used to create test executable programs. The test executable programs are evaluated against pass/fail criteria. The results of these evaluations are used to isolate the problematic binary file or set of files. The process is continued iteratively until the problematic file is determined. According to one embodiment the two compiling environments may be different modes of a given compiler.Type: GrantFiled: December 13, 2000Date of Patent: December 30, 2003Assignee: Intel CorporationInventors: Cigdem Y. Milobinski, David L. Kreitzer, Max W. Gravitt
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Publication number: 20020108105Abstract: An automated method for determining problematic binary files. A group of source code files is compiled using two different compiling environments. One of the compiling environments yields a failing set of binary files (i.e., the resultant executable program exhibits problematic behavior). The other compiling environment yields a passing set of binary files (i.e., the resultant executable program does not exhibit problematic behavior). Complementary sets of files, containing some passing files and some failing files, are used to create test executable programs. The test executable programs are evaluated against pass/fail criteria. The results of these evaluations are used to isolate the problematic binary file or set of files. The process is continued iteratively until the problematic file is determined. According to one embodiment the two compiling environments may be different modes of a given compiler.Type: ApplicationFiled: December 13, 2000Publication date: August 8, 2002Inventors: Cigdem Y. Milobinski, David L. Kreitzer, Max W. Gravitt