Abstract: A hybrid cache/SIRO buffer system includes a latch array for storing data words corresponding to system addresses; read command generator circuitry for launching data read commands to a memory system; a write pointer; write circuitry for storing data arriving from the memory system into the latch array at the location indicated by the write pointer; lowest and highest pointers for indicating the locations in the latch array corresponding to a lowest and a highest system address for which a read command has been launched; read circuitry for retrieving data from the latch array randomly; and control circuitry. Responsive to a first read request by a host system, the system begins retrieving data from memory beginning with an address equal to or close to the address associated with the first read request; then it speculatively reads ahead. As read requests from the host system continue to be processed by the system, more speculative reads are executed until the buffer is nearly full of data.

Abstract: A system is provided for achieving high speed data transfers from a host memory to an ancillary processor, where the ancillary processor is preferably a geometry accelerator of a graphics machine. In accordance with a preferred embodiment, the system includes at least one memory segment having at least one enable bit and a starting address. The system further includes a data transfer queue defined in a portion of the host memory beginning at the starting location, where the data transfer queue has at least one header portion and at least one data portion, the header portion including at least one data ready bit that is indicative of whether the associated block of data is ready to be transferred to the ancillary processor.

Abstract: A color graphics pipeline has a separate encoder with a dither table for processing each color value in pixel data received from a host processor or rasterizer. The encoders modify color values and dither noise values and also combine both positive and negative dither noise values with the color values, for independent optimization of each color and for better edge detection in a color recovery filter within a decoder of the pipeline. Each encoder comprises the following elements. A comparator mechanism compares a color value with a predetermined cutoff value. A dither table provides dither noise values. An offset mechanism modifies the dither noise values to derive a modified dither noise value when the color value is greater than or equal to the predetermined cutoff value. An aliasing mechanism aliases the color value with other color values below the predetermined cutoff value to derive an aliased color value when the color value is less than the predetermined cutoff value.

Abstract: A non-linear digital-to-analog converter (non-linear "DAC") and method are disclosed for scaling a digital input value by a non-integer and producing an analog output. The digital input value is multiplied by a non-integer, and the integer portion of the result is fed to a linear DAC to produce a linear analog output. At least one of the bits of the integer portion of the result is decoded, and at least one compensation value is generated responsive to the decoding. The compensation value is added to the linear analog output and represents the fractional portion of the result of scaling the digital input value by the non-integer. A method is also disclosed for utilizing the non-linear DAC for error compensation in a computer graphics system. Color intensity values are scaled up by a non-integer greater than one. A first analog output is generated proportional to the integer portion of the result.

Abstract: A color graphics pipeline has a separate encoder with a dither table for processing each color value in pixel data received from a host processor or rasterizer. The encoders modify color values and dither noise values and also combine both positive and negative dither noise values with the color values, for independent optimization of each color and for better edge detection in a color recovery filter within a decoder of the pipeline. Each encoder comprises the following elements. A comparator mechanism compares a color value with a predetermined cutoff value. A dither table provides dither noise values. An offset mechanism modifies the dither noise values to derive a modified dither noise value when the color value is greater than or equal to the predetermined cutoff value. An aliasing mechanism aliases the color value with other color values below the predetermined cutoff value to derive an aliased color value when the color value is less than the predetermined cutoff value.

Abstract: Highly purified brominated aromatic compounds such as decabromodiphenyl ether, pentabromophenol, and the like may be obtained by grinding the crude brominated product to provide particles predominantly less than about 20 microns in diameter and thereafter heating the crude ground brominated product for a time and at a temperature in order to effect substantial removal of the bromine and hydrogen bromide impurities therefrom. Optionally, the product may be ground a second time after the heating step to optimize product particle size and liberate residual impurities. The foregoing procedure is especially effective where the brominated compound is a thermally stable solid under the conditions of treatment and is substantially free from impurities containing aliphatic and alicyclic hydrocarbon groups.